EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 308
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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- Download datasheet (32Mb)
8–30
Stratix IV Clocking
Figure 8–23. LVDS/DPA Clocks in the Stratix IV Device Family with Center PLLs
Figure 8–24. LVDS/DPA Clocks in the Stratix IV Device Family with Center and Corner PLLs
Stratix IV Device Handbook Volume 1
2
4
4
2
4
4
4
2
2
4
4
2
2
4
The left and right PLLs feed into the differential transmitter and receive channels
through the LVDS and DPA clock network. The center left and right PLLs can clock
the transmitter and receive channels above and below them. The corner left and right
PLLs can drive I/Os in the banks adjacent to them.
Figure 8–23
information about PLL clocking restrictions, refer to
Guidelines” on page
Figure 8–24
more information about PLL clocking restrictions, refer to
Guidelines” on page
LVDS
Clock
LVDS
Clock
LVDS
LVDS
Clock
Clock
PLL_L2
PLL_L3
Center
Center
PLL_L2
PLL_L3
PLL_L4
Center
Center
Corner
Corner
PLL_L1
Clock
Clock
Clock
Clock
DPA
DPA
DPA
DPA
shows center PLL clocking in the Stratix IV device family. For more
shows center and corner PLL clocking in the Stratix IV device family. For
8–38.
8–38.
Quadrant
Quadrant
Quadrant
Quadrant
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Quadrant
Quadrant
Quadrant
Quadrant
“Differential Pin Placement
Clock
Clock
Clock
Clock
DPA
DPA
DPA
DPA
PLL_R1
PLL_R2
PLL_R3
PLL_R2
PLL_R3
PLL_R4
“Differential Pin Placement
Corner
Center
Center
Corner
Center
Center
February 2011 Altera Corporation
LVDS
Clock
LVDS
Clock
LVDS
Clock
LVDS
Clock
4
4
4
2
2
4
2
2
4
4
2
4
2
4
Stratix IV Clocking
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