EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 348

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

10–14
Figure 10–5. FPP Configuration Timing Waveform with Decompression or Design Security Feature Enabled
Notes to
(1) Use this timing waveform when you have enabled the decompression and/or design security features.
(2) The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels.
(3) After power-up, the Stratix IV device holds nSTATUS low for the time of the POR delay.
(4) After power-up, before and during configuration, CONF_DONE is low.
(5) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(6) DATA[7..0] are available as user I/O pins after configuration except for some exceptions on Stratix IV GT devices. The state of these pins
(7) If needed, you can pause DCLK by holding it low. When DCLK restarts, the external host must provide data on the DATA[7..0] pins prior to
Table 10–5. FPP Timing Parameters for Stratix IV Devices with the Decompression and/or Design Security Features
Enabled
Stratix IV Device Handbook Volume 1
t
t
t
t
t
t
Symbol
CF2CD
CF2ST0
CFG
STATUS
CF2ST1
CF2CK
CONF_DONE
When nCONFIG is pulled low, a reconfiguration cycle begins.
depends on the dual-purpose pin settings.
sending the first DCLK rising edge.
nSTATUS (3)
INIT_DONE
DATA[7..0]
nCONFIG
Figure
User I/O
(Note
DCLK
nCONFIG low to CONF_DONE
low
nCONFIG low to nSTATUS low
nCONFIG low pulse width
nSTATUS low pulse width
nCONFIG high to nSTATUS
high
nCONFIG high to first rising
edge on DCLK
(4)
10–5:
1),
t
t
(2)
CFG
CF2CD
Parameter
t
CF2ST1
t
Figure 10–5
MAX II device as an external host. This waveform shows the timing when you have
enabled the decompression and/or design security features.
Table 10–5
when you enable the decompression and/or the design security features.
CF2ST0
(Part 1 of 2)
t
CF2CK
t
ST2CK
t
STATUS
t
High-Z
DSU
1
2
Byte 0
t
lists the timing parameters for Stratix IV devices for an FPP configuration
DH
shows the timing waveform for an FPP configuration when using a
3
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
4
Stratix IV
1
(7)
t
CH
2
t
Byte 1
CLK
t
t
CL
DH
3
Stratix IV
Minimum
4
500
—
—
10
—
(8)
2
(7)
Stratix IV
Byte 2
(9)
1
Stratix IV
Byte (n-1)
(7)
3
4
Maximum
Stratix IV
Fast Passive Parallel Configuration
Byte n
500
500
800
800
April 2011 Altera Corporation
—
—
(8)
t
CD2UM
(3)
(4)
Stratix IV
(5)
(6)
(9)
User Mode
User Mode
(Note
1),
Units
ns
ns
μ s
μ s
μ s
μ s
(2)