EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 225

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Table 7–1. Stratix IV DQS/DQ Bus Mode Pins
Table 7–2. Number of DQS/DQ Groups in Stratix IV Devices per Side (Part 1 of 3)
February 2011 Altera Corporation
×4
×8/×9
×16/×18
×32/×36
×32/×36
Notes to
(1) The QVLD pin is not used in the ALTMEMPHY megafunction.
(2) This represents the maximum number of DQ pins (including parity, data mask, and QVLD pins) connected to the DQS bus network with
(3) Two ×4 DQS/DQ groups are stitched to make a ×8/×9 group so there are a total of 12 pins in this group.
(4) Four ×4 DQS/DQ groups are stitched to make a ×16/×18 group.
(5) Eight ×4 DQS/DQ groups are stitched to make a ×32/×36 group.
(6) The DM pin can be supported if differential DQS is not used and the group does not have additional signals.
(7) These ×32/×36 DQS/DQ groups are available in EP4SGX290, EP4SGX360, and EP4SGX530 devices in 1152- and 1517-pin FineLine BGA
(8) There are 40 pins in each of these DQS/DQ groups. The BWSn pins cannot be placed within the same DQS/DQ group as the write data pins
EP4SGX70
EP4SGX110
EP4SGX180
EP4SGX230
EP4SGX290
EP4SGX360
EP4SE230
EP4SE360
single-ended DQS signaling. When you use differential or complementary DQS signaling, the maximum number of data per group decreases
by one. This number may vary per DQS/DQ group in a particular device. Check the pin table for the exact number per group. For DDR3, DDR2,
and DDR interfaces, the number of pins is further reduced for an interface larger than ×8 due to the need of one DQS pin for each ×8/×9 group
that is used to form the x16/×18 and ×32/×36 groups.
packages. There are 40 pins in each of these DQS/DQ groups.
because of insufficient pins available.
Mode
Device
(3)
Table
(4)
(5)
(7)
7–1:
DQSn Support
780-pin
FineLine BGA
780-pin
FineLine BGA
780-pin
FineLine BGA
The Stratix IV device family supports DQS and DQ signals with DQ bus modes of ×4,
×8/×9, ×16/×18, or ×32/×36, although not all devices support DQS bus mode
×32/×36. When any of these pins are not used for memory interfacing, you can use
them as user I/Os. In addition, you can use any DQSn or CQn pins not used for
clocking as DQ (data) pins.
including the DQS/CQ and DQSn/CQn pin pair.
Table 7–2
device. For a more detailed listing of the number of DQS/DQ groups available per
bank in each Stratix IV device, see
represent the die-top view of the Stratix IV device.
Package
Yes
Yes
Yes
Yes
Yes
lists the number of DQS/DQ groups available per side in each Stratix IV
CQn Support
Top/Bottom
Top/Bottom
Top/Bottom
Left/Right
Left/Right
Yes
Yes
Yes
Yes
Right
No
Side
Left
Table 7–1
Parity or DM
×4
(Optional)
14
17
18
14
17
0
0
No
No
(2)
Yes
Yes
Yes
Figure 7–3
(6)
(8)
lists pin support per DQS/DQ bus mode,
×8/×9
6
8
0
0
8
6
8
(Optional)
through
QVLD
Yes
Yes
Yes
Yes
No
×16/×18
(1)
(Note 1)
2
2
0
0
2
2
2
Figure
Stratix IV Device Handbook Volume 1
Number of
per Group
Data Pins
16 or 18
32 or 36
32 or 36
Typical
×32/×36
7–19. These figures
8 or 9
4
0
0
0
0
0
0
0
(3)
Number of
Maximum
per Group
Data Pins
Figure 7–3
Figure 7–5
Figure 7–4
Refer to:
11
23
47
39
(2)
5
7–5