EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 718

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

2–46
Figure 2–26. Receiver Datapath Clocking in x4 Bonded Channel Configuration Without Deskew FIFO
Note to
(1) The red lines represent the FPGA fabric-Transceiver interface clock, the green lines represent the low-speed parallel clock, the dark red lines
Stratix IV Device Handbook Volume 2: Transceivers
represent the parallel recovered clock, and the blue lines represent the serial recovered clock.
Figure
rx_coreclk[0]
rx_coreclk[2]
rx_coreclk[1]
rx_coreclk[3]
Fabric
FPGA
FPGA Fabric_Transceiver
2–26:
Interface Clock
coreclkout
PCIe ×4 functional modes supports the ×4 bonded channel configuration without
deskew FIFO.
Figure 2–26
configurations without deskew FIFO.
x4 Bonded Channel Configuration Without Deskew FIFO
hard IP
hard IP
hard IP
hard IP
PCIe
PCIe
PCIe
PCIe
/2
Reference
Reference
Clock
Clock
Input
Input
Interface
Interface
Interface
Interface
PIPE
PIPE
PIPE
PIPE
shows the receiver datapath clocking in ×4 channel bonding
Compensation
Compensation
Compensation
Compensation
RX Phase
RX Phase
RX Phase
RX Phase
CMU1 PLL
CMU1 PLL
CMU0 PLL
FIFO
FIFO
FIFO
FIFO
Ordering
Ordering
Ordering
Ordering
Byte
Byte
Byte
Byte
Divider
CMU1
Clock
Divider
CMU0
Serializer
Serializer
Clock
Serializer
Serializer
Byte
/2
/2
Byte
/2
De-
Byte
De-
De-
Byte
/2
De-
CMU0 Channel
CMU1 Channel
Low-Speed Parallel Clock from CMU0 Clock Divider
Low-Speed Parallel Clock from CMU0 Clock Divider
Low-Speed Parallel Clock from CMU0 Clock Divider
Low-Speed Parallel Clock from CMU0 Clock Divider
Decoder
Decoder
Decoder
8B/10B
Decoder
8B/10B
8B/10B
8B/10B
Match
Match
Match
FIFO
FIFO
Rate
Rate
FIFO
Match
Rate
FIFO
Rate
Low-Speed Parallel Clock
Ch2 Parallel Recovered Clock
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
Ch3 Parallel Recovered Clock
Ch0 Parallel Recovered Clock
Receiver Channel PCS
Chapter 2: Transceiver Clocking in Stratix IV Devices
Ch1 Parallel Recovered Clock
Aligner
Aligner
Aligner
Word
Aligner
Word
Word
Word
Channel 3
Channel 0
Channel 2
Channel 1
Transceiver Channel Datapath Clocking
Receiver Channel PMA
Receiver Channel PMA
Serializer
Receiver Channel PMA
Serializer
Serializer
Receiver Channel PMA
Serializer
De-
De-
De-
February 2011 Altera Corporation
De-
CDR
CDR
Serial Recovered Clock
CDR
Serial Recovered Clock
Serial Recovered Clock
Serial Recovered Clock
CDR
Input Reference Clock
Input Reference Clock
(Note 1)
Input Reference Clock
Input Reference Clock