EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 632
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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1–188
Figure 1–154. Stratix IV GX and GT Transceiver Configured in Basic (PMA Direct) Mode
Note to
(1) The grayed out blocks shown in
Stratix IV Device Handbook Volume 2: Transceivers
as transceiver channels in PMA direct mode only.
Fabric
FPGA
Figure
1–154:
1
Figure 1–154
(PMA Direct) functional mode. The grayed out blocks indicate areas that are not
active in this mode.
The grayed out blocks shown in
Therefore, the CMU channels can be configured to operate as transceiver channels in
PMA Direct mode only.
In Basic (PMA Direct) Mode, you can configure the transceiver channel in two main
configurations:
■
■
You can configure the transceiver in Basic (PMA Direct) ×1/ ×N mode by setting the
appropriate sub-protocol in the Which sub protocol will you be using? field. You can
select single-width or double-width by selecting Single/Double in the What is the
deserializer block width? field in the ALTGX MegaWizard Plug-In Manager.
In single-width mode, the PMA-PLD interface is 8 bit/10 bit wide; whereas in
double-width mode, the PMA-PLD interface is 16 bit/20 bit wide.
Basic (PMA Direct) ×1 configuration
Basic (PMA Direct) ×N configuration
Figure 1–154
Compensation
shows the Stratix IV GX and GT transceiver configured in Basic
wrclk
TX Phase
FIFO
are not available in the CMU channels. Therefore, the CMU channels can be configured to operate
rdclk
wrclk
Byte Serializer
Receiver Channel PCS
Transmitter Channel PCS
Figure 1–154
rdclk
Chapter 1: Transceiver Architecture in Stratix IV Devices
are not available in the CMU channels.
8B/10B Encoder
February 2011 Altera Corporation
Transceiver Block Architecture
Transmitter Channel
Receiver Channel
PMA
PMA
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