EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 266

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

7–46
Figure 7–26. Avoiding Glitch on a Non-Consecutive Read Burst Waveform
Stratix IV Device Handbook Volume 1
Postamble Enable
dqsenable
DQS
DQS Postamble Circuitry
For external memory interfaces that use a bidirectional read strobe such as in DDR3,
DDR2, and DDR SDRAM, the DQS signal is low before going to or coming from a
high-impedance state. The state in which DQS is low, just after a high-impedance
state, is called the preamble; the state in which DQS is low, just before it returns to a
high-impedance state, is called the postamble. There are preamble and postamble
specifications for both read and write operations in DDR3, DDR2, and DDR SDRAM.
The DQS postamble circuitry ensures that data is not lost if there is noise on the DQS
line during the end of a read operation that occurs while DQS is in a postamble state.
Stratix IV devices have dedicated postamble registers that you can control to ground
the shifted DQS signal used to clock the DQ input registers at the end of a read
operation. This ensures that any glitches on the DQS input signals during the end of a
read operation that occurs while DQS is in a postamble state do not affect the DQ IOE
registers.
In addition to the dedicated postamble register, Stratix IV devices also have an HDR
block inside the postamble enable circuitry. Use these registers if the controller is
running at half the frequency of the I/Os.
Using the HDR block as the first stage capture register in the postamble enable
circuitry block is optional. The HDR block is clocked by the half-rate
resynchronization clock, which is the output of the I/O clock divider circuit (shown in
Figure 7–31 on page
that is used to avoid postamble glitches from a previous read burst on a
non-consecutive read burst. This scheme allows a half-a-clock cycle latency for
dqsenable assertion and zero latency for dqsenable de-assertion, as shown in
Figure
7–26.
7–50). There is an AND gate after the postamble register outputs
Chapter 7: External Memory Interfaces in Stratix IV Devices
Postamble
Stratix IV External Memory Interface Features
Postamble glitch
February 2011 Altera Corporation
Preamble
Delayed by
1/2T logic