EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 916
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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5–70
Figure 5–36. Connecting ALTGX and ALTGX_RECONFIG Instances with EyeQ Enabled
Stratix IV Device Handbook Volume 2: Transceivers
reconfig_mode_sel[3:0]
ctrl_writedata[15:0]
ALTGX_RECONFIG Instance
ctrl_address[15:0]
EyeQ Control
Figure 5–36
instances and the EyeQ control logic in the dynamic reconfiguration controller.
Controlling the EyeQ Hardware
The EyeQ hardware is controlled by writing to the EyeQ registers using EyeQ
interface registers in the ALTGX_RECONFIG instance.
memory of the 16-bit EyeQ registers.
Table 5–13. EyeQ Register Mapping
0×0
0×1
Block
ctrl_readdata[15:0]
ctrl_write
Address
ctrl_waitrequest
ctrl_read
error
shows the connections between the EyeQ hardware in the ALTGX
busy
reconfig_fromgxb[17:0]
reconfig_togxb[3:0]
■
■
■
■
Bit[0]—0/1: Disable/Enable EyeQ feature
Bit [15:1]—15'b000000000000000
Bits [5:0]—EyeQ phase step value. Refer to
phase step encoding.
Bits [15:6]—10'b0000000000
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Receiver Channel 0
EyeQ Hardware
ALTGX Instance
Description
Dynamic Reconfiguration Modes Implementation
Table 5–13
February 2011 Altera Corporation
Table 5–14
lists the register
for the EyeQ
rx_datain[0]
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