EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 563

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–100. Transceiver Configurations in Basic Double-Width Mode with a 20-Bit PMA-PCS Interface for Stratix IV GX
Devices
Notes to
(1) The maximum data rate specification shown in
(2) The byte ordering block is available only if you select the word alignment pattern length of 20 bits.
February 2011 Altera Corporation
other speed grades offered, refer to the
(FPGA Fabric-Transceiver
(FPGA Fabric-Transceiver
Figure
(1)
(1)
Interface Clock Cycles)
Interface Clock Cycles)
TX PCS Latency
Interface Frequency
RX PCS Latency
Interface Frequency
Interface Frequency
Data Rate (Gbps)
Low-Latency PCS
Data Rate (Gbps
Channel Bonding
Rate Match FIFO
Encoder /Decoder
Interface Width
(Pattern Length )
FPGA Fabric -
FPGA Fabric -
Interface Width
FPGA Fabric -
Byte Ordering
Transceiver
Transceiver
Word Aligner
Byte SerDes
Transceiver
Interface Width
PMA-PCS
1–100:
( MHz )
PMA-PCS
Functional
8B/10B
Modes
)
Figure 1–100
double-width functional mode with a 20-bit PMA-PCS interface.
Figure 1–101
double-width functional mode with a 20-bit PMA-PCS interface.
Disabled
Disabled
10 - 12
8-bit
20-bit
1.0 -
6.5
50 -
325
5 - 6
Single
Width
Disabled
Disabled
6.5 - 8.5
Disabled
10-bit
212.5
4 - 5.5
40-bit
25 -
Basic
Enabled
1.0 –
8.5
16-bit
Enabled (2)
6.5 - 8.5
212.5
4 - 5.5
40-bit
Manual Alignment
25 -
DC and Switching Characteristics
Double
(7-, 10-, 20-bit)
Width
shows Stratix IV GX transceiver configurations allowed in Basic
shows Stratix IV GT transceiver configurations allowed in Basic
20-bit
Disabled
Disabled
10 - 12
16-bit
5 - 6
Stratix IV GX Configurations
1.0 –
50 -
250
Figure 1–100
5.0
Disabled
6.5 - 8. 5
Disabled
4 - 5.5
212.5
10-bit
PIPE
32-bit
25 -
Enabled
8.5
1.0 –
Enabled
Enabled (2)
6.5 - 8. 5
XAUI
10-bit
4 - 5.5
212.5
32-bit
25 -
is valid only for the -2 (fastest) speed grade devices. For data rate specifications for
GIGE
10-bit
Disabled
Disabled
22 - 26
1.0 –
16-bit
5 - 6
5.0
Disabled
50 -
250
Enabled
Protocol
SRIO
10-bit
Enabled
Disabled
13 - 16
212.5
1.0 –
8.5
32-bit
4 - 5.5
25 -
chapter.
SONET
/SDH
8-bit
Basic Double Width
20-bit PMA-PCS
Interface Width
16-bit
Disabled
Disabled
(OIF)
1.0 – 8.5
10 - 12
CEI
20-bit
50 -
325
1.0 -
6.5
5 - 6
x1, x4, x8
Disabled
Disabled
10-bit
6.5 - 8. 5
SDI
Disabled
Enabled
4 - 5.5
(7-, 10-, 20-bit)
212.5
8.5
40-bit
1.0 –
25 -
Bit-Slip
Stratix IV Device Handbook Volume 2: Transceivers
10-Bit
Disabled
Disabled
10 - 12
Deterministic
1.0 –
16-bit
5 - 6
50 -
5.0
250
Latency
Disabled
Enabled
20-Bit
6.5 - 8. 5
Enabled
Disabled
4 - 5.5
8.5
32-bit
212.5
1.0 –
25 -
Disabled
Disabled
20-bit
4 - 5
1.0 -
6.5
50 -
3 - 4
325
Disabled
Disabled
Disabled
Enabled
Enabled
Disabled
212.5
4 - 5.5
1.0 –
40-bit
3 - 4.5
25 -
8.5
1–119