EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 884

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

5–38
Table 5–9. tx_datainfull[43:0] FPGA Fabric-Transceiver Channel Interface Signal Descriptions (Part 1 of 2)
Stratix IV Device Handbook Volume 2: Transceivers
8-bit FPGA fabric-transceiver Channel
Interface
10-bit FPGA fabric-transceiver
Channel Interface
16-bit FPGA fabric-transceiver
Channel Interface with PCS-PMA set
to 16/20 bits
16-bit FPGA fabric-transceiver
Channel Interface with PCS-PMA set
to 8/10 bits
20-bit FPGA fabric-transceiver
Channel Interface with PCS-PMA set
to 20 bits
FPGA Fabric-Transceiver Channel
Interface Description
tx_datainfull[7:0]: 8-bit data (tx_datain)
The following signals are used only in 8B/10B modes:
tx_datainfull[8]: Control bit (tx_ctrlenable)
tx_datainfull[9]
Transmitter force disparity Compliance (PCIe) (tx_forcedisp) in all modes
except PCIe. For PCIe mode, (tx_forcedispcompliance) is used.
tx_datainfull[10]: Forced disparity value (tx_dispval)
tx_datainfull[9:0]: 10-bit data (tx_datain)
Two 8-bit Data (tx_datain)
tx_datainfull[7:0] - tx_datain (LSByte) and tx_datainfull[18:11] -
tx_datain (MSByte)
The following signals are used only in 8B/10B modes:
tx_datainfull[8] - tx_ctrlenable (LSB) and tx_datainfull[19] -
tx_ctrlenable (MSB)
Force Disparity Enable
tx_datainfull[9] - tx_forcedisp (LSB) and tx_datainfull[20] -
tx_forcedisp (MSB)
Force Disparity Value
tx_datainfull[10] - tx_dispval (LSB) and tx_datainfull[21] -
tx_dispval (MSB)
Two 8-bit Data (tx_datain)
tx_datainfull[7:0] - tx_datain (LSByte) and tx_datainfull[29:22] -
tx_datain (MSByte)
The following signals are used only in 8B/10B modes:
Two Control Bits (tx_ctrlenable)
tx_datainfull[8] - tx_ctrlenable (LSB) and tx_datainfull[30] -
tx_ctrlenable (MSB)
Force Disparity Enable
For non-PIPE:
tx_datainfull[9] - tx_forcedisp (LSB) and tx_datainfull[31] -
tx_forcedisp (MSB)
For PCIe:
tx_datainfull[9] - tx_forcedispcompliance (LSB) and
tx_datainfull[31] - tx_forcedispcompliance (MSB)
Force Disparity Value
tx_datainfull[10] - tx_dispval (LSB) and tx_datainfull[32] -
tx_dispval (MSB)
Two 10-bit Data (tx_datain)
tx_datainfull[9:0] - tx_datain (LSByte) and tx_datainfull[20:11] -
tx_datain (MSByte)
Transmit Signal Description (Based on Stratix IV GX Supported FPGA
Fabric-Transceiver Channel Interface Widths)
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
February 2011 Altera Corporation
(Note 1)