EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 1144

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–62
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
Programmable Output Buffer Delay
Table 1–52
of the output buffer. The default delay is 0 ps.
Table 1–52. Programmable Output Buffer Delay
D
Note to
(1) You can set the programmable output buffer delay in the Quartus II software by setting the Output Buffer Delay
OUTBUF
Control assignment to either positive, negative, or both edges, with the specific values stated here (in ps) for the
Output Buffer Delay assignment.
Table
Symbol
lists the delay chain settings that control the rising and falling edge delays
1–52:
Rising and/or falling edge
delay
Parameter
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
(Note 1)
0 (default)
Typical
100
150
50
April 2011 Altera Corporation
Unit
ps
ps
ps
ps
I/O Timing