EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 471

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–23. Transmitted Output Data When tx_digitalreset is Asserted
February 2011 Altera Corporation
1
1
dataout[19:10]
tx_digitalreset
dataout[9:0]
Altera does not recommend sending invalid control words to the 8B/10B encoder.
The tx_digitalreset signal resets the 8B/10B encoder. During reset, the running
disparity and data registers are cleared. Also, the 8B/10B encoder outputs a K28.5
pattern with proper disparity continuously until tx_digitalreset goes low. The
inputs from the tx_datain and tx_ctrlenable ports are ignored during the reset
state. After reset, the 8B/10B encoder starts the LSByte with a negative disparity (RD-)
and the MSByte with a positive disparity (RD+) and transmits six K28.5 code groups
(three on the LSByte and three on the MSByte encoder) for synchronizing before it
starts encoding and transmitting data.
If the tx_digitalreset signal is asserted, the downstream 8B/10B decoder receiving
the data might get synchronization or disparity errors.
Figure 1–23
(tx_digitalreset is high), a K28.5- on LSB and K28.5+ on MSB is sent continuously
until tx_digitalreset is low. Due to pipelining of the TX channel, there will be some
“don’t cares” (10'hxxx) until the first K28.5 is sent
cares”, but the number of “don’t cares” can vary). Both the LSByte and MSByte
transmit three K28.5s before the data at the tx_datain port is encoded and sent out.
Controlling Running Disparity
After power on or reset, the 8B/10B encoder has a negative disparity and chooses the
10-bit code from the RD- column (refer to the 8B/10B encoder specification for the
RD+ and RD- column values). The ALTGX MegaWizard Plug-In Manager provides
the tx_forcedisp and tx_dispval ports to control the running disparity of the output
from the 8B/10B encoder. These ports are available only in Basic single-width and
Basic double-width modes.
A high value on the tx_forcedisp port is the control signal to the disparity value of
the output data. The disparity value (RD+ or RD-) is indicated by the value on the
tx_dispval port. If the tx_forcedisp port is low, tx_dispval is ignored and the
current running disparity is not altered. Forcing disparity can either maintain the
current running disparity calculations if the forced disparity value (on the tx_dispval
bit) matches the current running disparity, or flip the current running disparity
calculations if it does not. If the forced disparity flips the current running disparity,
the downstream 8B/10B decoder might detect a disparity error.
clock
Reset Condition
k28.5-
k28.5+
shows the reset behavior of the 8B/10B encoder. When in reset
k28.5-
k28.5+
k28.5-
k28.5+
xxx
xxx
xxx
xxx
xxx
xxx
k28.5-
k28.5+
Stratix IV Device Handbook Volume 2: Transceivers
(Figure 1–23
k28.5-
k28.5+
k28.5+
k28.5-
shows six “don’t
Dx.y+
Dx.y-
1–27