EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 1020

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EP4SE530H40I3

Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er

Specifications of EP4SE530H40I3

Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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2–2
Figure 2–1. Flow Chart of the Different Stages in a Transceiver-Based Design
Stratix IV Device Handbook Volume 3
Add Altera Simulation Library Files
megafunction-generated wrapper file
Include the Stratix IV GX ALTGX
Functional Simulation
megafunction-generated
wrapper file (.v or .vhd)
Simulate the Design
ALTGX_Reconfig
If used,
and
Yes
Create a Dynamic Reconfiguration
Create Reset and Control Logic
Create Data Processing Logic
ALTGX_Reconfig MegaWizard
Select Options in the Dynamic
Create Timing Constraints
Reconfiguration Controller
Integrate the Design
Synthesize the Design
Create Clock Grouping
Constraints if Required
Create Transceiver
Create Pin and OCT
Compile the Design
Controller using the
Implementation
Compilation
Require SignalTap
Reconfiguration
Architecture
for Verification?
Is Simulation
Assignments
Power Supplies
Is Dynamic
Configuration
Required ?
Instances
Required ?
Specification
Transceiver
(if required)
Clocking
Device
Yes
No
No
Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
No
Yes
SignalTap II Logic Analyzer
(.stp) in the Compilation
Include SignalTap file
Add signals to
Verification
February 2011 Altera Corporation

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