EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 105
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SE230F29C3N PDF datasheet #6
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Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
February 2011 Altera Corporation
To implement this complex multiplication within the DSP block, the real part
((a × c) – (b × d)) is implemented using two multipliers feeding one subtractor block
while the imaginary part ((a × d) + (b × c)) is implemented using another two
multipliers feeding an adder block.
multiplication. This mode automatically assumes all inputs are using signed
numbers.
Figure 4–16. Complex Multiplier Using Two-Multiplier Adder Mode
A
C
B
D
clock[3..0]
ena[3..0]
aclr[3..0]
Half-DSP Block
signa
signb
Figure 4–16
shows an 18-bit complex
Stratix IV Device Handbook Volume 1
36
36
Imaginary Part
A
A
x
x
Real Part
C
D
B
B
x
x
D
C
4–25
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