EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 94

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

4–14
Stratix IV Device Handbook Volume 1
Rounding and Saturation Stage
Second Adder and Output Registers
1
The rounding and saturation logic units are located at the output of the 44-bit
second-stage adder (the rounding logic unit followed by the saturation logic unit).
There are two rounding and saturation logic units per half DSP block. The input to the
rounding and saturation logic unit can come from one of the following stages:
■
■
■
■
These stages are described in
page
The rounding and saturation logic unit is controlled by the dynamic rounding and
saturate signals, respectively. A logic 1 value on the rounding and/or saturate
signals enables the rounding and/or saturate logic unit, respectively.
You can use the rounding and saturation logic units together or independently.
The second adder register and output register banks are two banks of 44-bit registers
that you can combine to form larger 72-bit banks to support 36 × 36 output results.
The outputs of the different stages in the Stratix IV devices are routed to the output
registers through an output selection unit. Depending on the operational mode of the
DSP block, the output selection unit selects whether the outputs of the DSP blocks
comes from the outputs of the multiplier block, first-stage adder, pipeline registers,
second-stage adder, or the rounding and saturation logic unit. The output selection
unit is set automatically by the software, based on the DSP block operational mode
you specified, and has the option to either drive or bypass the output registers. The
exception is when you use the block in shift mode, in which case you dynamically
control the output-select multiplexer directly.
When the DSP block is configured in chained cascaded output mode, both of the
second-stage adders are used. Use the first one for performing a four-multiplier
adder; use the second for the chainout adder.
The outputs of the four-multiplier adder are routed to the second-stage adder
registers before they enter the chainout adder. The output of the chainout adder goes
to the regular output register bank. Depending on the configuration, you can route
the chainout results to the input of the next half block’s chainout adder input or to the
general fabric (functioning as regular output registers). For more information, refer to
“Stratix IV Operational Mode Descriptions” on page
Output of the multiplier (independent multiply mode in 18 × 18)
Output of the first-stage adder (two-multiplier adder)
Output of the pipeline registers
Output of the second-stage adder (four-multiplier adder and multiply-accumulate
mode in 18 × 18)
4–15.
“Stratix IV Operational Mode Descriptions” on
4–15.
Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV DSP Block Resource Descriptions
February 2011 Altera Corporation