EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 827

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 4: Reset Control and Power Down in Stratix IV Devices
Transceiver Reset Sequences
February 2011 Altera Corporation
As shown in
manual lock mode:
1. After power up, assert pll_powerdown for a minimum period of t
2. Keep the tx_digitalreset, rx_analogreset, rx_digitalreset, and
3. After the transmitter PLL locks, as indicated by the pll_locked signal going high
4. Wait for at least t
5. De-assert rx_digitalreset at least t
time between markers 1 and 2).
rx_locktorefclk signals asserted and the rx_locktodata signal de-asserted
during this time period. After you de-assert the pll_powerdown signal, the
transmitter PLL starts locking to the transmitter input reference clock.
(marker 3), de-assert tx_digitalreset. For receiver operation, wait for the busy
signal to be de-asserted. At this point rx_analogreset is de-asserted. When
rx_analogreset is de-asserted, the receiver CDR starts locking to the receiver
input reference clock because rx_locktorefclk is asserted.
rx_pll_locked signal goes high, then de-assert the rx_locktorefclk signal. At the
same time, assert the rx_locktodata signal (marker 8). At this point, the receiver
CDR enters lock-to-data mode and the receiver CDR starts locking to the received
data.
after asserting the rx_locktodata signal.
Figure
4–11, perform the following reset procedure for the receiver in
LTR_LTD_Manual
(the time between markers 7 and 8) after the
LTD_Manual
Stratix IV Device Handbook Volume 2: Transceivers
(the time between markers 8 and 9)
pll_powerdown
(the
4–21