EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 882
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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5–36
Figure 5–21. Option 3 for Receiver Core Clocking (Channel and CMU PLL Reconfiguration Mode)
Stratix IV Device Handbook Volume 2: Transceivers
FPGA Fabric
rx_clkout[1]
rx_clkout[0]
Low-speed parallel clock generated by the local divider of the transceiver
High-speed serial clock generated by the CMU0 PLL
High-speed serial clock generated by the CMU1 PLL
Figure 5–21
receiver channels of a transceiver block.
This section describes the ALTGX MegaWizard Plug-In Manager settings related to
the FPGA fabric-transceiver channel interface data width when you select and
activate channel and CMU PLL reconfiguration mode. You must set up the FPGA
fabric-transceiver channel interface data width when functional mode reconfiguration
involves:
■
■
You can set up the FPGA fabric-transceiver channel interface data width by enabling
the Channel Interface option in the Modes screen.
Enable the Channel Interface option if the reconfiguration channel has:
■
■
changes in the FPGA fabric-transceiver channel data width
enables and disables the static PCS blocks of the transceiver channel
changed the FPGA fabric-transceiver channel interface data width
changed the input control signals and output status signals
FPGA Fabric-Transceiver Channel Interface Selection
OR
OR
shows the respective rx_clkout of each channel clocking the respective
Transceiver Block
TX0 (2 Gbps)
TX1 (2 Gbps)
RX0
RX1
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
CMU0 PLL
CMU1 PLL
February 2011 Altera Corporation
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