EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 612

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–168
Figure 1–134. Automatic Ordered Set Generation
Stratix IV Device Handbook Volume 2: Transceivers
1
Ordered Set
tx_datain [ ]
tx_dataout
Table 1–63. GIGE Ordered Sets (Part 2 of 2)
Idle Ordered-Set Generation
The IEEE 802.3 specification requires the GIGE PHY to transmit idle ordered sets (/I/)
continuously and repetitively whenever the GMII is idle. This ensures that the
receiver maintains bit and word synchronization whenever there is no active data to
be transmitted.
In GIGE functional mode, any /Dx.y/ following a /K28.5/ comma is replaced by the
transmitter with either a /D5.6/ (/I1/ ordered set) or a /D16.2/ (/I2/ ordered set),
depending on the current running disparity. The exception is when the data following
the /K28.5/ is /D21.5/ (/C1/ ordered set) or /D2.2/ (/C2/) ordered set. If the
running disparity before the /K28.5/ is positive, an /I1/ ordered set is generated. If
the running disparity is negative, a /I2/ ordered set is generated. The disparity at the
end of a /I1/ is the opposite of that at the beginning of the /I1/. The disparity at the
end of a /I2/ is the same as the beginning running disparity (right before the idle
code). This ensures a negative running disparity at the end of an idle ordered set. A
/Kx.y/ following a /K28.5/ is not replaced.
Note that /D14.3/, /D24.0/, and /D15.8/ are replaced by /D5.6/ or /D16.2/ (for
/I1/, /I2/ ordered sets). /D21.5/ (part of the /C1/ order set) is not replaced.
Figure 1–134
Note to
(1) Two data code groups representing the Config_Reg value.
clock
Code
/I1/
/I2/
/R/
/S/
/T/
/V/
/I/
Table
K28.5
Dx.y
1–63:
Error_Propagation
shows the automatic idle ordered set generation.
Start_of_Packet
Carrier_Extend
D14.3
K28.5
End_of_Packet
Encapsulation
Ordered Set
/I1/
IDLE 1
IDLE 2
IDLE
K28.5
D5.6
D24.0
K28.5
/I2/
K28.5
D16.2
Number of Code
Groups
D15.8
K28.5
Chapter 1: Transceiver Architecture in Stratix IV Devices
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2
2
1
1
1
1
/I2/
K28.5
D16.2
Correcting /I1/, Preserving /I2/
D21.5
K28.5
/C2/
February 2011 Altera Corporation
D21.5
/K28.5/D16.2
Transceiver Block Architecture
/K28.5/D5.6
Dx.y
Encoding
/K23.7/
/K27.7/
/K29.7/
/K30.7/
—