EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 279
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #3
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
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SIV51008-3.2
Overview
Stratix IV Device Handbook Volume 1
February 2011
February 2011
SIV51008-3.2
This chapter describes the significant advantages of the high-speed differential I/O
interfaces and the dynamic phase aligner (DPA) over single-ended I/Os and their
contribution to the overall system bandwidth achievable with Stratix
references to Stratix IV devices in this chapter apply to Stratix IV E, GT, and GX
devices.
The Stratix IV device family consists of the Stratix IV E (Enhanced) devices without
high-speed clock data recovery (CDR) based transceivers, Stratix IV GT devices with
up to 48 CDR-based transceivers running up to 11.3 Gbps, and Stratix IV GX devices
with up to 48 CDR-based transceivers running up to 8.5 Gbps.
The following sections describe the Stratix IV high-speed differential I/O interfaces
and DPA:
■
■
■
■
■
■
■
■
■
■
■
All Stratix IV E, GX, and GT devices have built-in serializer/deserializer (SERDES)
circuitry that supports high-speed LVDS interfaces at data rates of up to 1.6 Gbps.
SERDES circuitry is configurable to support source-synchronous communication
protocols such as Utopia, Rapid I/O, XSBI, small form factor interface (SFI), serial
peripheral interface (SPI), and asynchronous protocols such as SGMII and Gigabit
Ethernet.
The Stratix IV device family has the following dedicated circuitry for high-speed
differential I/O support:
■
■
■
“Locations of the I/O Banks” on page 8–3
“LVDS Channels” on page 8–4
“LVDS SERDES” on page 8–8
“ALTLVDS Port List” on page 8–9
“Differential Transmitter” on page 8–11
“Differential Receiver” on page 8–17
“LVDS Interface with the Use External PLL Option Enabled” on page 8–26
“Left and Right PLLs (PLL_Lx and PLL_Rx)” on page 8–29
“Stratix IV Clocking” on page 8–30
“Source-Synchronous Timing Budget” on page 8–31
“Differential Pin Placement Guidelines” on page 8–38
Differential I/O buffer
Transmitter serializer
Receiver deserializer
8. High-Speed Differential I/O Interfaces
and DPA in Stratix IV Devices
®
IV FPGAs. All
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