EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 295

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Receiver
Differential Receiver
February 2011 Altera Corporation
1
The Stratix IV device family has a dedicated circuitry to receive high-speed
differential signals in row I/Os.
Stratix IV receiver. The receiver has a differential buffer and left and right PLLs that
can be shared between the transmitter and receiver, a DPA block, a synchronizer, a
data realignment block, and a deserializer. The differential buffer can receive LVDS,
mini-LVDS, and RSDS signal levels, which are statically set in the Quartus II software
Assignment Editor.
The left and right PLL receives the external clock input and generates different phases
of the same clock. The DPA block chooses one of the clocks from the left and right PLL
and aligns the incoming data on each channel. The synchronizer circuit is a 1 bit wide
by 6 bit deep FIFO buffer that compensates for any phase difference between the DPA
clock and the data realignment block. If necessary, the user-controlled data
realignment circuitry inserts a single bit of latency in the serial bit stream to align to
the word boundary. The deserializer includes shift registers and parallel load
registers, and sends a maximum of 10 bits to the internal logic.
The Stratix IV device family supports three different receiver modes:
■
■
■
The physical medium connecting the transmitter and receiver LVDS channels may
introduce skew between the serial data and the source-synchronous clock. The
instantaneous skew between each LVDS channel and the clock also varies with the
jitter on the data and clock signals as seen by the receiver. The three different modes—
non-DPA, DPA, and soft-CDR—provide different options to overcome skew between
the source synchronous clock (non-DPA, DPA) /reference clock (soft-CDR) and the
serial data.
Only non-DPA mode requires manual skew adjustment.
Non-DPA mode allows you to statically select the optimal phase between the source
synchronous clock and the received serial data to compensate skew. In DPA mode,
the DPA circuitry automatically chooses the best phase to compensate for the skew
between the source synchronous clock and the received serial data. Soft-CDR mode
provides opportunities for synchronous and asynchronous applications for
chip-to-chip and short reach board-to-board applications for SGMII protocols.
“Non-DPA Mode” on page 8–22
“DPA Mode” on page 8–24
“Soft-CDR Mode” on page 8–25
Figure 8–12
shows the hardware blocks of the
Stratix IV Device Handbook Volume 1
8–17