EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 125

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
Clock Networks in Stratix IV Devices
February 2011 Altera Corporation
Clock Sources Per Quadrant
Clock Regions
1
There are 26 section clock (SCLK) networks available in each spine clock that can
drive six row clocks in each logic array block (LAB) row, nine column I/O clocks, and
three core reference clocks. The SCLKs are the clock resources to the core functional
blocks, PLLs, and I/O interfaces of the device.
be driven by the GCLK, RCLK, PCLK, or the PLL feedback clock networks in each
spine clock.
A spine clock is another layer of routing below the GCLKs, RCLKs, and PCLKs before
each clock is connected to clock routing for each LAB row. The settings for spine
clocks are transparent to all users. The Quartus II software automatically routes the
spine clock based on the GCLK, RCLK, and PCLKs.
Figure 5–9. Hierarchical Clock Networks per Spine Clock
Notes to
(1) The GCLK, RCLK, PCLK, and PLL feedback clocks share the same routing to the SCLKs. The total number of clock
(2) There are up to 16 PCLKs that can drive the SCLKs in each spine clock in the largest device.
(3) There are up to 22 RCLKs that can drive the SCLKs in each spine clock in the largest device.
(4) The PLL feedback clock is the clock from the PLL that drives into the SCLKs.
(5) The column I/O clock is the clock that drives the column I/O core registers and I/O interfaces.
(6) The core reference clock is the clock that feeds into the PLL as the PLL reference clock.
(7) The row clock is the clock source to the LAB, memory blocks, and row I/O interfaces in the core row.
Stratix IV devices provide up to 104 distinct clock domains (16 GCLKs + 88 RCLKs) in
the entire device. You can use these clock resources to form the following types of
clock regions:
■
■
■
To form the entire device clock region, a source (not necessarily a clock signal) drives a
GCLK network that can be routed through the entire device. This clock region has the
maximum delay when compared with other clock regions, but allows the signal to
reach every destination within the device. This is a good option for routing global
reset and clear signals or routing clocks throughout the device.
PLL feedback clock
Entire device
Regional
Dual-regional
resources must not exceed the SCLK limits in each region to ensure successful design fitting in the Quartus II
software.
Figure
5–9:
GCLK
RCLK
PCLK
(4)
16
16 (2)
22 (3)
3
SCLK
Figure 5–9
26
(Note 1)
shows that the SCLKs can
Stratix IV Device Handbook Volume 1
9
3
6
Column I/O clock
Core reference clock
Row clock
(7)
5–9
(5)
(6)