EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 922

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

5–76
Figure 5–39. AEQ Timing Diagram in One-Time Adaptation Mode
Dynamic Reconfiguration Controller Port List
Table 5–16. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 1 of 13)
Stratix IV Device Handbook Volume 2: Transceivers
Clock Inputs to the ALTGX_RECONFIG Instance
reconfig_clk
logical_channel_address[]
reconfig_mode_sel[3:0]
Port Name
write_all
One Time Mode for a Single Channel
Stratix IV GX and GT devices only support one-time adaptation mode for the AEQ
feature.
After assertion of the write_all signals, the dynamic reconfiguration controller
performs the following steps sequentially:
1. Powers down the receiver buffer and performs offset calibration for the target
2. Powers up the receiver buffer and runs the convergence algorithm to set the
3. Puts the AEQ circuitry in stand-by mode maintaining the converged equalization
If you observe bit errors over time with the converged equalization settings, you can
re-initiate one-time adaptation by following the timing diagram shown in
Figure
powered down for offset calibration, thereby interrupting the link during this time.
Table 5–16
reconfiguration controller.
busy
channel.
appropriate equalization settings.
setting. In standby mode, no further adaptation occurs.
5–39. Each time you re-initiate one-time adaptation, the receiver buffer is
Figure 5–39
lists the input control ports and output status ports of the dynamic
4’b1001
4 (logical channel 4)
Output
Input/
Input
shows the AEQ timing diagram in this mode.
Offset calibration and AEQ convergence
The frequency range of this clock depends on the following
transceiver channel configuration modes:
■
■
■
By default, the Quartus II software assigns a global clock resource
to this port. This clock must be a free-running clock sourced from
an I/O clock pin. Do not use dedicated transceiver REFCLK pins or
any clocks generated by transceivers.
Receiver only (37.5 MHz to 50 MHz)
Receiver and Transmitter (37.5 MHz to 50 MHz)
Transmitter only (2.5 MHz to 50 MHz)
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Description
Dynamic Reconfiguration Controller Port List
indicates AEQ convergence
and entry into stand-by mode
February 2011 Altera Corporation
(Note
3),
(4)