EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 1026

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
Implementation and Integration
February 2011 Altera Corporation
Create Reset and Control Logic
Create Data Processing and Other User Logic
f
f
For more information about using the signals, refer to the
Stratix IV Devices
The reset sequence is important for initializing the transceiver functional blocks to
proper operating condition. Altera recommends a reset sequence for different
transceiver configurations and protocol functional modes. The ALTGX MegaWizard
Plug-In Manager provides the tx_digitalreset, rx_analogreset, rx_digitalreset,
and pll_powerdown signals to reset the different functional blocks of the transceiver.
You can reset the CMU PLL or the ATX PLL (based on your selection) using the
pll_powerdown signal. For transceiver instances that share the same CMU PLL or
ATX PLL, the pll_powerdown port of these instances must be driven by the same logic.
For more information about reset sequences, refer to the
in Stratix IV Devices
A typical transceiver-based design consists of custom data processing and other user
logic that must be implemented in the FPGA fabric based on your application
requirements. In addition to application-specific logic, for specific transceiver
configurations, you may need additional logic to interface with the transceivers. This
section provides examples of such logic.
PPM Detector When the Receiver CDR Is Used in Manual Lock Mode
Each receiver channel contains a clock data recovery (CDR) that you can use in
automatic or manual lock mode.
If you use the receiver CDR in manual lock mode, you can control the timing of the
CDR to lock to the input reference clock using the rx_locktorefclk port or lock to the
recovered data using the rx_locktodata port.
When you use the receiver CDR in manual lock mode, you may need to implement
the PPM detector in the FPGA fabric to determine the PPM difference between the
upstream transmitter and the Stratix IV GX receiver.
Synchronization State Machine in Manual Word Alignment Mode
Each receiver channel contains a synchronization state machine in the PCS that you
can enable in certain functional modes. The synchronization state machine triggers
the loss of synchronization status to the FPGA fabric based on invalid 8B/10B code
groups.
However, the synchronization state machine in the PCS is not available in some
functional modes. You may need to implement custom logic in the FPGA fabric to
indicate the loss-of-synchronization status of the received data.
chapter.
chapter.
Reset Control and Power Down
Dynamic Reconfiguration in
Stratix IV Device Handbook Volume 3
2–8