EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 460

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–16
Transceiver Block Architecture
Figure 1–11. Top-Level View of a Transceiver Block
Stratix IV Device Handbook Volume 2: Transceivers
Transceiver Block
Transceiver Block
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
QL1
QL0
Figure 1–11
Each transceiver block has the following components:
1. Four full-duplex (transmitter and receiver) transceiver channels that support serial
2. Two CMU channels—CMU0 and CMU1 channels—that provide the high-speed serial
3. Central control unit (CCU) that implements the XAUI state machine for
data rates from 600 Mbps to 8.5 Gbps in Stratix IV GX devices and 600 Mbps to
11.3 Gbps in Stratix IV GT devices. For more information, refer to
Channel Architecture” on page
and low-speed parallel clock to the transceiver channels. For more information,
refer to
XGMII-to-PCS code group conversion, XAUI deskew state machine, shared
control signal generation block, PCIe rateswitch controller block, and reset control
logic
■
■
The shared control signal generation block provides control signals to the
transceiver channels in bonded functional modes, such as XAUI, PCIe, and
Basic ×4.
The PCIe rateswitch controller block controls the rateswitch circuit in the CMU0
channel in ×4 configurations. In PCIe ×8 configuration, the PCIe rateswitch
controller block of the CCU in the master transceiver block is active. For more
information, refer to
“CMU Channel Architecture” on page
shows the transceiver block architecture of Stratix GX and GT devices.
Transceiver Block
Transceiver Block
QR1
QR0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
“PCIe Gen2 (5 Gbps) Support” on page
1–17.
Chapter 1: Transceiver Architecture in Stratix IV Devices
Unit (CCU)
Central
Control
Transceiver Channel 3
Transceiver Channel 2
Transceiver Channel 1
Transceiver Channel 0
3
Transceiver Block
1–100.
CMU1 Channel
CMU0 Channel
February 2011 Altera Corporation
1
Transceiver Block Architecture
1
1
1
1–140.
2
2
“Transceiver