EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 158

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

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Stratix IV Device Handbook Volume 1
f
Manual Clock Switchover
In manual clock switchover mode, the clkswitch signal controls whether inclk0 or
inclk1 is selected as the input clock to the PLL. By default, inclk0 is selected. A
low-to-high transition on clkswitch and clkswitch being held high for at least three
inclk cycles initiates a clock switchover event. You must bring clkswitch back low
again in order to perform another switchover event in the future. If you do not require
another switchover event in the future, you can leave clkswitch in a logic high state
after the initial switch. Pulsing clkswitch high for at least three inclk cycles performs
another switchover event. If inclk0 and inclk1 are different frequencies and are
always running, the clkswitch minimum high time must be greater than or equal to
three of the slower frequency inclk0 or inclk1 cycles.
diagram of the manual switchover circuit.
Figure 5–37. Manual Clock Switchover Circuitry in Stratix IV PLLs
For more information about PLL software support in the Quartus II software, refer to
the
Guidelines
When implementing clock switchover in Stratix IV PLLs, use the following
guidelines:
■
■
■
Automatic clock switchover requires that the inclk0 and inclk1 frequencies be
within 100% (2×) of each other. Failing to meet this requirement causes the
clkbad[0] and clkbad[1] signals to not function properly.
When using manual clock switchover, the difference between inclk0 and inclk1
can be more than 100% (2×). However, differences in frequency, phase, or both, of
the two clock sources will likely cause the PLL to lose lock. Resetting the PLL
ensures that the correct phase relationships are maintained between the input and
output clocks.
1
Applications that require a clock switchover feature and a small frequency drift
must use a low-bandwidth PLL. The low-bandwidth PLL reacts more slowly than
a high-bandwidth PLL to reference input clock changes. When switchover
happens, a low-bandwidth PLL propagates the stopping of the clock to the output
more slowly than a high-bandwidth PLL. However, be aware that the
low-bandwidth PLL also increases lock time.
Phase-Locked Loop (ALTPLL) Megafunction User
clkswitch
inclk0
inclk1
Both inclk0 and inclk1 must be running when the clkswitch signal goes
high to initiate the manual clock switchover event. Failing to meet this
requirement causes the clock switchover to not function properly.
Control Logic
Clock Switch
muxout
n Counter
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
refclk
Guide.
Figure 5–37
February 2011 Altera Corporation
PFD
shows a block
PLLs in Stratix IV Devices
fbclk