EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 679
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SE530H40I3
Manufacturer:
ALTERA
Quantity:
325
Company:
Part Number:
EP4SE530H40I3N
Manufacturer:
SHARP
Quantity:
1 200
Company:
Part Number:
EP4SE530H40I3N
Manufacturer:
ALTERA
Quantity:
490
Part Number:
EP4SE530H40I3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
- Current page: 679 of 1154
- Download datasheet (32Mb)
Chapter 2: Transceiver Clocking in Stratix IV Devices
Input Reference Clocking
set_instance_assignment -name INPUT_TERMINATION OFF -to <refclk_pin_name>
February 2011 Altera Corporation
f
1
1
refclk0 and refclk1 Pins
Each transceiver block has two dedicated refclk pins that you can use to drive the
CMU PLL, receiver CDR, or both, input reference clocks. Each of the two CMU PLLs
and four receiver CDRs within a transceiver block can derive its input reference clock
from either the refclk0 or refclk1 pin.
The refclk pins provide the cleanest input reference clock path to the
CMU/ATX PLLs when compared with other input reference clock sources. Altera
recommends using the refclk pins to drive the CMU PLL input reference clock for
improved transmitter output jitter performance.
Table 2–4
on the refclk pins.
For specifications regarding the input frequency supported by the refclk pins, refer
to the
Table 2–4. Electrical Specifications for the Input Reference Clock
If you select the HCSL I/O standard for the PCIe reference clock, add the following
assignment to your project quartus settings file (.qsf):
■
■
■
■
■
■
■
PCI Express
Notes to
(1) In PCIe mode, you have the option of selecting the HCSL standard for the reference clock if compliance to the PCIe
(2) Termination values supported are the same as the Receiver pin differential on-chip termination resistors specified
(3) For an example termination scheme, refer to
GIGE
XAUI
Serial RapidIO
SONET/SDH
SDI
(OIF) CEI PHY Interface
Basic
protocol is required. You can select this I/O standard option only if you configured the transceiver in PCIe functional
mode. For more information, refer to
in the
DC and Switching Characteristics for Stratix IV Devices
Table
Protocol
DC and Switching Characteristics for Stratix IV Devices
lists the electrical specifications for the input reference clock signal driven
®
2–4:
(PCIe)
®
■
■
■
■
■
■
■
■
■
■
■
■
■
1.2-V PCML, 1.4 PCML
1.4-V PCML
1.5-V PCML
2.5-V PCML
Differential LVPECL
LVDS
1.2-V PCML, 1.4 PCML
1.4-V PCML
1.5-V PCML
2.5-V PCML
Differential LVPECL
LVDS
HCSL
Figure 2–5 on page 2–8.
(1)
I/O Standard
Figure 2–5 on page
chapter.
Stratix IV Device Handbook Volume 2: Transceivers
2–8.
Coupling
chapter.
AC
AC
DC
Termination
Off-chip
On-chip
On-chip
(2)
(2)
(3)
2–7
Related parts for EP4SE530H40I3
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: