EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 1029

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
Compilation
February 2011 Altera Corporation
Report Files
f
The Quartus II software provides a report file in the synthesis, fitter, map, placement,
and assembler stages. The report file provides useful information on the device and
transceiver configuration generated by the Quartus II software. This section only
describes the reports provided in the fitter stage. To access the report, click on the
Processing menu, select the Compilation Report option and expand the Fitter tab.
Fitter Summary
The fitter summary provides high-level information on the FPGA fabric resources and
transceiver channels used by your design. For example, to ensure that the Quartus II
software has created the number of transceiver channels as specified in your design,
refer to the GXB Receiver channels and GXB Transmitter channels field at the bottom
of the report. For detailed information on resource utilization, expand the Fitter tab.
Pin-Out File
Select the Pin-Out file option under the Fitter tab. The Quartus II software displays
the I/O standards and bank numbers of all the pins (used and unused) needed to
connect to the board. The Quartus II software also generates a PIN file (.pin) with the
above information. Altera recommends using the .pin as a guideline. Use the pin
connection guidelines for board layout.
For more information about pin connection guidelines for board layout, refer to
Stratix IV GX and Stratix IV E Device Family Pin Connection
Resource Section
Expand the Resource Section option under the Fitter tab to view the following tabs:
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■
■
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You can use the report file to verify whether the transceiver settings (for example,
data rate), are generated per your settings in the ALTGX MegaWizard Plug-In
Manager.
The GXB Transmitter channel tab—Provides generated settings for all the
transmitter channels instantiated in your design.
The GXB Transmitter PLL tab—Provides generated settings for all the transmitter
PLLs instantiated in your design.
The GXB Receiver channel tab—Provides generated settings for all the receiver
channels instantiated in your design.
The Global and other fast signals tab—Displays the list of clock and other signals
in your design that are assigned to the global and regional clock resources.
Guidelines.
Stratix IV Device Handbook Volume 3
2–11