EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 317

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EP4SE530H40I3

Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er

Specifications of EP4SE530H40I3

Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Pin Placement Guidelines
February 2011 Altera Corporation
You do not need a separation if a single left and right PLL is driving the DPA-enabled
channels as well as DPA-disabled channels.
Figure 8–31. Corner and Center Left and Right PLLs Driving DPA-Enabled Differential I/Os in the
Same Bank
Left
Left /Right PLL
Reference
DPA -enabled
DPA - enabled
DPA - enabled
DPA - enabled
DPA - enabled
DPA-enabled
DPA-enabled
DPA -enabled
DPA- enabled
Reference
CLK
/
Diff I/O
Corner
Right PLL
Diff I/O
Diff I/O
Diff I/O
Diff I/O
CLK
Center
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Channel for Buffer
Channels
Channels
driven by
driven by
Left/Right
One Unused
Left/Right
Corner
Center
PLL
PLL
Stratix IV Device Handbook Volume 1
8–39

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