EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 782
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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3–28
Stratix IV Device Handbook Volume 2: Transceivers
Figure 3–13
gxb_powerdown and pll_powerdown ports for channels 0 to 4 and channels 5 and 6 are
driven from the same logic.
Figure 3–13. Combined Channels After Compilation for Example 5
If you connect each of the seven bits of the gxb_powerdown and pll_powerdown ports to
different reset control logic, the Quartus II software requires seven transceiver blocks
to combine the seven channels in the instance.
shows the conditions after compilation. In this example, the
RX
Transceiver Block1
RX
RX
RX
RX
RX
RX
Transceiver Block0
Inst0: Channel 3
Inst0: Channel 2
Inst0: Channel 4
Inst0: Channel 5
Inst0: Channel 0
Inst0: Channel 1
Inst0: Channel 6
Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
TX
TX
TX
TX
TX
TX
TX
Combining Transceiver Channels in Basic (PMA Direct) Configurations
CMU PLL
CMU PLL
February 2011 Altera Corporation
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