EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 318
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SE230F29C3N PDF datasheet #6
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8–40
Stratix IV Device Handbook Volume 1
Using Both Center Left and Right PLLs
You can use both center left and right PLLs to drive DPA-enabled channels
simultaneously, as long as they drive these channels in their adjacent banks only, as
shown in
If one of the center left and right PLLs drives the top and bottom banks, you cannot
use the other center left and right PLL to drive differential channels, as shown in
Figure
If the top PLL_L2 and PLL_R2 drives DPA-enabled channels in the lower differential
bank, the PLL_L3 and PLL_R3 cannot drive DPA-enabled channels in the upper
differential banks and vice versa. In other words, the center left and right PLLs cannot
drive cross-banks simultaneously, as shown in
Figure 8–32. Center Left and Right PLLs Driving DPA-Enabled Differential I/Os
8–32.
Figure
(PLL_L2/PLL_R2)
(PLL_L3/PLL_R3)
Left/Right PLL
Left/Right PLL
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
Reference
Reference
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Center
Center
8–32.
CLK
CLK
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Figure
8–33.
Differential Pin Placement Guidelines
(PLL_L3/PLL_R3)
(PLL_L2/PLL_R2)
February 2011 Altera Corporation
Left/Right PLL
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
Reference
Left/Right PLL
DPA-enabled
DPA-enabled
DPA-enabled
Reference
CLK
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Center
Center
CLK
Unused
PLL
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