EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 409

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 11: SEU Mitigation in Stratix IV Devices
User Mode Error Detection
February 2011 Altera Corporation
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A single 16-bit CRC calculation is done on a per-frame basis. After it has finished the
CRC calculation for a frame, the resulting 16-bit signature is hex 0000 if there are no
CRAM bit errors detected in a frame by the error detection circuitry and the output
signal CRC_ERROR is 0. If a CRAM bit error is detected by the circuitry within a frame in
the device, the resulting signature is non-zero. This causes the CRC engine to start
searching for the error bit location.
Error detection in Stratix IV devices calculates CRC check bits for each frame and
pulls the CRC_ERROR pin high when it detects bit errors in the chip. Within a frame, it
can detect all single-bit, double-bit, and three-bit errors. The probability of more than
three CRAM bits being flipped by an SEU event is very low. In general, for all error
patterns the probability of detection is 99.998%.
The CRC engine reports the bit location and determines the type of error for all
single-bit errors and over 99.641% of double-adjacent errors. The probability of other
error patterns is very low and report of the location of bit flips is not guaranteed by
the CRC engine.
You can also read-out the error bit location through the JTAG and the core interface.
Shift these bits out through either the SHIFT_EDERROR_REG JTAG instruction or the core
interface before the CRC detects the next error in another frame. If the next frame also
has an error, you must shift these bits out within the amount of time of one frame CRC
verification. You can choose to extend this time interval by slowing down the error
detection clock frequency, but this slows down the error recovery time for the SEU
event. For the minimum update interval for Stratix IV devices, refer to
page
previous error location and error message is overwritten by the new information. The
CRC circuit continues to run, and if an error is detected, you must decide whether to
complete a reconfiguration or to ignore the CRC error.
The error detection logic continues to calculate the CRC_ERROR and 16-bit signatures for
the next frame of data regardless if any error has occurred in the current frame or not.
You need to monitor these signals and take the appropriate actions if a soft error
occurs.
The error detection circuitry in Stratix IV devices uses a 16-bit CRC-ANSI standard
(16-bit polynomial) as the CRC generator.
The computed 16-bit CRC signature for each frame is stored in the registers within the
core. The total storage register size is 16 (the number of bits per frame) × the number
of frames.
The Stratix IV device error detection feature does not check memory blocks and I/O
buffers. Thus, the CRC_ERROR signal might stay solid high or low depending on the
error status of the previously checked CRAM frame. The I/O buffers are not verified
during error detection because these bits use flipflops as storage elements that are
more resistant to soft errors when compared with CRAM cells. The support parity bits
of MLAB, M9K, and M144K are used to check the contents of the memory blocks for
any errors. The M144K TriMatrix memory block has a built-in error correction code
block that checks and corrects the errors in the block.
For more information, refer to the
Devices
11–9. If these bits are not shifted out before the next error location is found, the
chapter.
TriMatrix Embedded Memory Blocks in Stratix IV
Stratix IV Device Handbook Volume 1
Table 11–6 on
11–3