EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 863

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
Figure 5–8. Method 2—Read Transaction Waveform
Note to
(1) To read the current V
February 2011 Altera Corporation
Figure
5–8:
1
rx_tx_duplex_sel [1:0]
tx_vodctrl [5:0] (1)
OD
reconfig_clk
Figure 5–8
channels 1 and 2 prior to the read transaction are 3'b001 and 3'b010, respectively.
Simultaneous write and read transactions are not allowed.
Method 3—Using Individual Control Signals for Each Channel
You can optionally use Method 3 to individually reconfigure the PMA controls of each
transceiver channel.
When you disable the Use the same control signal for all channels option, the PMA
control ports for the write transaction are also separate for each channel. For example,
if you have two channels, tx_vodctrl is 6 bits wide (tx_vodctrl[2:0] corresponds to
channel 1 and tx_vodctrl[5:3] corresponds to channel 2).
The width of the PMA control ports for a read transaction are always separate for each
channel (the same as the PMA control ports, as explained in
Same Control Signals for All Channels” on page
values in channel 2, observe the values in tx_vodctrl_out[5:3].
data_valid
busy
read
shows the read transaction waveform. The transmit V
2’b00
6’b000000
2’b10 (transmitter portion only)
6’bXXXXXX
5–15.)
Stratix IV Device Handbook Volume 2: Transceivers
“Method 2—Using the
6’b010001
OD
settings written in
5–17