EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 137

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
Table 5–8. PLL Features in Stratix IV Devices (Part 2 of 2)
Figure 5–18. PLL Locations in Stratix IV Devices
February 2011 Altera Corporation
PLL cascading
Compensation modes
PLL drives LVDSCLK and LOADEN
VCO output drives the DPA clock
Phase shift resolution
Programmable duty cycle
Output counter cascading
Input clock switchover
Notes to
(1) While there is pin compatibility, there is no hard IP block placement compatibility.
(2) General purpose I/O pins cannot drive the PLL clock input pins.
(3) Provided input clock jitter is within input jitter tolerance specifications.
(4) The dedicated path between adjacent PLLs is not available on L1, L4, R1, and R4 PLLs.
(5) The smallest phase shift is determined by the voltage-controlled oscillator (VCO) period divided by eight. For degree increments, the Stratix IV
device can shift all output frequencies in increments of at least 45
divide parameters.
Left/Right PLLs
Left/Right PLLs
Table
5–8:
Feature
PLL_L1_CLK
PLL_L4_CLK
CLK[0..3]
Figure 5–18
L1
L2
L3
L4
shows the location of PLLs in Stratix IV devices.
Through GCLK and RCLK and a dedicated
Top/Bottom PLLs
Top/Bottom PLLs
All except LVDS clock network
Stratix IV Top/Bottom PLLs
path between adjacent PLLs
Down to 96.125 ps
compensation
CLK[12..15]
CLK[4..7]
Q1
Q4
B1 B2
T1
°
Yes
Yes
Yes
No
No
. Smaller degree increments are possible depending on the frequency and
(Note 1)
T2
Q2
Q3
Top/Bottom PLLs
Top/Bottom PLLs
(5)
dedicated path between adjacent PLLs
All except external feedback mode
Through GCLK and RCLK and
when using differential I/Os
R1
R2
R3
R4
Stratix IV Left/Right PLLs
Down to 96.125 ps
Stratix IV Device Handbook Volume 1
PLL_R1_CLK
CLK[8..11]
PLL-R4_CLK
Yes
Yes
Yes
Yes
Yes
(4)
Left/Right PLLs
Left/Right PLLs
(5)
5–21