EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 593

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Table 1–56. Transceiver Clock Frequencies Signaling Rates in PCIe ×8 Mode
February 2011 Altera Corporation
FPGA Fabric-Transceiver Interface
Low-Speed Parallel Clock
Parallel Recovered Clock
High-Speed Serial Clock
Serial Recovered Clock
Transceiver Clocks
Clock
In PCIe ×8 mode configured at 5 Gbps data rate, when the PCIe rateswitch controller
sees a transition on the rateswitch signal, it sends the pcie_gen2switch control signal
to the PCIe clock switch circuitry in the CMU0 clock divider of the master transceiver
block and the receiver CDR in all eight bonded channels to switch to the instructed
signaling rate. A low-to-high transition on the rateswitch signal initiates a Gen1
(2.5 Gbps) to Gen2 (5 Gbps) signaling rateswitch. A high-to-low transition on the
rateswitch signal initiates a Gen2 (5 Gbps) to Gen1 (2.5 Gbps) signaling rateswitch.
Table 1–56
2.5 Gbps and 5 Gbps signaling rates.
The PCIe clock switch circuitry in the CMU0 clock divider of the master transceiver
block performs the clock switch between 250 MHz and 500 MHz on the low-speed
parallel clock when switching between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) signaling
rates. It indicates successful completion of clock switch on the pcie_gen2switchdone
signal to the PCIe rateswitch controller. The PCIe rateswitch controller forwards the
clock switch completion status to the PCIe interface block. The PCIe interface block
communicates the clock switch completion status to the PHY-MAC layer by asserting
the pipephydonestatus signal of all eight bonded channels for one parallel clock
cycle.
lists the transceiver clock frequencies when switching between the
Switch (Low-to-High Transition on the
Gen1 (2.5 Gbps) to Gen 2 (5 Gbps)
250 MHz to 500 MHz
250 MHz to 500 MHz
125 MHz to 250 MHz
1.25 GHz to 2.5 GHz
1.25 GHz to 2.5 GHz
rateswitch Signal)
Stratix IV Device Handbook Volume 2: Transceivers
Switch (High-to-Low Transition on the
Gen2 (5 Gbps) to Gen1 (2.5 Gbps)
500 MHz to 250 MHz
500 MHz to 250 MHz
250 MHz to 125 MHz
2.5 GHz to 1.25 GHz
2.5 GHz to 1.25 GHz
rateswitch Signal)
1–149