EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 570

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–126
Figure 1–105. Block Diagram of the Deterministic Latency Option
Stratix IV Device Handbook Volume 2: Transceivers
(FPGA Fabric-Transceiver
(FPGA Fabric-Transceiver
Interface Frequency
Interface Clock Cycles)
Interface Clock Cycles)
Fabric-Transceiver
Interface Frequency
Fabric-Transceiver
Low-Latency PCS
Rate Match FIFO
Data Rate (Gbps)
Encoder/Decoder
Channel Bonding
TX PCS Latency
Interface Frequency
(Pattern Length)
Interface Width
RX PCS Latency
FPGA Fabric
Byte Ordering
Byte SerDes
Word Aligner
Transceiver
Interface Width
Functional
Data Rate
Functional
FPGA
(MHz)
PMA-PCS
8B/10B
FPGA
Mode
Modes
-
1
8-bit
Single
Width
Under the deterministic latency option, CPRI data rates can be implemented in
single-width mode with 8/10-bit channel width and double-width mode with
16/20-bit channel width options only.
deterministic latency option.
To implement CPRI/OBSAI using deterministic latency mode, Altera recommends
using configurations with the byte serializer/deserializer disabled.
10-Bit
Basic
16-Bit
Double
Width
Stratix IV GX and GT Configurations
20-Bit
10-Bit
PIPE
248.8 - 250 - GT
60 - 250 - GX
XAUI
10-Bit
2.488 -2.5 GT
0.6 - 2.5 GX
Disabled
Disabled
10-Bit
4
7
GIGE
10-Bit
Disabled
Disabled
124.4 - 187.5 - GT
30 - 187.5 - GX
2.488 - 3.75 GT
Protocol
0.6 - 3.75 GX
Disabled
SRIO
10-Bit
Enabled
20-Bit
SONET
600 Mbps -3.75 Gbps - GT
/SDH
8-Bit
0.6 - 3.75 Gbps - GX
Manual Alignment
Deterministic
Disabled
248.8 - 250 - GT
Latency
(10-Bit)
x1, x4
60 - 250 - GX
16-Bit
(OIF)
2.488 -2.5 GT
CEI
0.6 - 2.5 GX
Disabled
Disabled
8-Bit
Figure 1–105
4
7
10-Bit
Disabled
Enabled
SDI
124.4 - 187.5 - GT
Chapter 1: Transceiver Architecture in Stratix IV Devices
2.488 - 3.75 GT
30 - 187.5 - GX
0.6 - 3.75 GX
Enabled
Disabled
10
16-Bit
Deterministic
-Bit
Latency
20-Bit
shows the block diagram of the
124.4 - 325 - GT
50 - 325 - GX
2.488 - 6.5 GT
1.0 - 6.5 GX
Disabled
Disabled
20-Bit
4
8
Disabled
Disabled
62.2 - 212.5 - GT
25 - 212.5 - GX
February 2011 Altera Corporation
600 Mbps - 8.5 Gbps - GT
2.488 - 8.5 GT
1.0 - 8.5 GX
Enabled
0.6 - 8.5 Gbps - GX
Manual Alignment
Disabled
40-Bit
(10-Bit, 20-bit)
Deterministic
Disabled
Transceiver Block Architecture
Latency
x1, x4
124.4 - 250 - GT
2.488 - 5.0 GT
50 - 250 - GX
1.0 - 5.0 GX
Disabled
Disabled
16-Bit
4
8
Disabled
Enabled
2.488 - 8.5 GT
1.0 - 8.5 GX
62.2 - 212.5 - GT
Enabled
Disabled
25 - 212.5 - GX
32-Bit