EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 42

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EP4SE530H40I3

Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er

Specifications of EP4SE530H40I3

Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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0
2–6
Figure 2–5. High-Level Block Diagram of the Stratix IV ALM
Stratix IV Device Handbook Volume 1
datae0
datae1
dataf0
dataf1
dataa
datab
datad
datac
In addition to the adaptive LUT-based resources, each ALM contains two
programmable registers, two dedicated full adders, a carry chain, a shared arithmetic
chain, and a register chain. Through these dedicated resources, an ALM can
efficiently implement various arithmetic functions and shift registers. Each ALM
drives all types of interconnects: local, row, column, carry chain, shared arithmetic
chain, register chain, and direct link.
the Stratix IV ALM.
Combinational/Memory ALUT1
Combinational/Memory ALUT0
shared_arith_out
shared_arith_in
6-Input LUT
6-Input LUT
carry_in
carry_out
adder0
adder1
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
Figure 2–5
reg_chain_in
reg_chain_out
labclk
shows a high-level block diagram of
D
D
reg0
reg1
Q
Q
February 2011 Altera Corporation
To general or
To general or
To general or
To general or
local routing
local routing
local routing
local routing
Adaptive Logic Modules

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