EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 492

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–48
Table 1–23. Allowed DC-Coupling Scenarios for Stratix IV GT Devices (Part 1 of 2)
Stratix IV Device Handbook Volume 2: Transceivers
Stratix IV GT Transmitter
(1.4-V PCML)
Stratix IV GX Transmitter
(1.4-V PCML)
(Transmitter I/O Standard)
From
Figure 1–42
DC-coupled link.
Figure 1–42. LVDS Transmitter to Stratix IV GX Receiver (PCML)
Note to
(1) R
Table 1–22
Stratix IV GX receiver DC-coupled link.
Table 1–22. Settings for a LVDS transmitter to Stratix IV GX Receiver DC-Coupled Link
Stratix IV GT devices allow the high-speed links to be AC- or DC-coupled links
(AC-coupling allowed for the entire data rate range between 600 Mbps and
11.3 Gbps).
Table 1–23
Notes to
(1) When DC-coupling an LVDS transmitter to the Stratix IV GX receiver, use RX V
(2) Pending characterization.
Link Coupling for Stratix IV GT Devices
value RS to verify compliance with the LVDS specification.
S
is the parasitic resistance present in the on-chip RX termination and biasing circuitry.
Figure
RX V
Stratix IV GT Receiver
(1.4-V PCML)
Stratix IV GT Receiver
(1.4-V PCML)
Table
(Receiver I/O Standard)
1.1 V
lists the allowed transmitter and receiver settings in a LVDS transmitter to
lists the allowed DC-coupling scenarios for Stratix IV GT devices.
LVDS
Transmitter
CM
1–42:
shows the LVDS transmitter to Stratix IV GX receiver (PCML)
1–22:
To
Differential Termination
Receiver (Stratix IV GX) Settings
600 Mbps to 11.3 Gbps
600 Mbps to 8.5 Gbps
Physical Medium
Physical Medium
100 Ω
Data Rate Range
50-
RX Termination
Chapter 1: Transceiver Architecture in Stratix IV Devices
Ω
RX
V
CM
■
■
■
■
R
s
1.1 V
CM
TX V
RX V
TX V
RX V
February 2011 Altera Corporation
50-
RX Termination
(1)
= 1.1 V and series resistance
Ω
Transceiver Block Architecture
CM
CM
Stratix IV GX
Receiver
CM
CM
Conditions
= 0.65 V
= 0.65 V
= 0.82 V
= 0.82 V
R
(2)
S
(Note 1)