EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 730

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

2–58
Stratix IV Device Handbook Volume 2: Transceivers
Because all 16 channels are identical, using a single tx_clkout to clock the transmitter
phase compensation FIFO in all 16 channels results in only one global or regional
clock resource being used instead of four. To achieve this, you must choose the
transmitter phase compensation FIFO write clocks instead of the Quartus II software
automatic selection, as described in
FIFO Write Clock” on page
User-Selected Transmitter Phase Compensation FIFO Write Clock
The ALTGX MegaWizard Plug-In Manager provides an optional port named
tx_coreclk for each instantiated transmitter channel. If you enable this port, the
Quartus II software does not automatically select the transmitter phase compensation
FIFO write clock source. Instead, the signal that you drive on the tx_coreclk port of
the channel clocks the write side of its transmitter phase compensation FIFO.
Use the flexibility of selecting the transmitter phase compensation FIFO write clock to
reduce global and regional clock resource usage. You can connect the tx_coreclk
ports of all identical channels in your design and drive them using a common clock
driver that has 0 PPM frequency difference with respect to the FIFO read clocks of
these channels. Use the common clock driver to clock the transmitter data and control
logic in the FPGA fabric for all identical channels. This FPGA fabric-Transceiver
interface clocking scheme uses only one global or regional clock resource for all
identical channels in your design.
Example 5: Sixteen Identical Channels Across Four Transceiver Blocks
Figure 2–32
blocks. The tx_coreclk ports of all 16 transmitter channels are connected together
and driven by a common clock driver. This common clock driver also drives the
transmitter data and control logic of all 16 transmitter channels in the FPGA fabric.
You use only one global or regional clock resource with this clocking scheme,
compared to four global and regional clock resources needed without the tx_coreclk
ports (the Quartus II software-selected transmitter phase compensation FIFO write
clock).
shows 16 identical transmitter channels located across four transceiver
2–58.
“User-Selected Transmitter Phase Compensation
Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric-Transceiver Interface Clocking
February 2011 Altera Corporation