EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 670

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–226
Document Revision History
Table 1–81. Document Revision History (Part 1 of 2)
Stratix IV Device Handbook Volume 2: Transceivers
February 2011
March 2010
November 2009
Date
Version
Table 1–80. Reference Information (Part 3 of 3)
Table 1–81
4.0
4.2
4.1
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■
■
■
■
■
■
■
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■
■
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Applied new template.
Updated the “Overview”,
Coupling for Stratix IV GX and GT
Generation”,
in the Receiver Buffer and Receiver
“Word-Alignment-Based Byte
“Loopback
and
Updated
Figure
Figure
Figure
Figure
Updated
Table
Table
Updated chapter title.
Applied new template.
Minor text edits.
Added two references to the beginning of the chapter.
Updated the “Configuring CMU Channels for Clock Generation” section.
Updated Figure 1–101.
Minor text edits.
Added “Adaptive Equalization (AEQ)”, “EyeQ”, “SATA and SAS Options”, “Deterministic
Latency Mode”, “CPRI and OBSAI”, and “Reference Information” sections.
Added Figure 1–91, Figure 1–93, Figure 1–95, and Figure 1–97.
Added Stratix IV GT device information.
Updated Figures.
Updated Tables.
Re-organized chapter information.
Minor text edits.
Terms Used in this Chapter
lists the revision history for this chapter.
“PCI Express Electrical Gold Test with Compliance Base Board (CBB)”
1–17,
1–43,
1–7,
1–64,
1–97,
1–112, and
Word Aligner
XAUI Mode
Figure
Table
Modes”,
Figure
Table
Table
Figure
“Configuring CMU Channels as Transceiver
Figure
1–2,
1–1,
1–18,
1–45,
Figure
1–8,
Table
1–76,
1–99,
“Reverse Serial
Figure
Figure
Table
Table
“Transceiver Block
1–157.
1–3,
Figure
Figure
1–2,
1–19,
1–68,
Ordering”,
1–9,
Table
Figure
1–83,
1–100,
Devices”,
CDR”,
Figure
Loopback”,
1–4,
Table
Table
Changes
Figure 1–84,Figure
Chapter 1: Transceiver Architecture in Stratix IV Devices
1–3,
Figure
“SATA and SAS
Table
1–21,
1–70,
“Modes of Operation of the
1–10,
“Configuring CMU Channels for Clock
Architecture”,
Figure
1–5,
1–101,
“Input Signals to the Calibration
Table
Table
Figure
1–4,
Useful Reference Points
Table
1–23,
1–74, and
Figure
1–11,
Figure
Channels”,
Options”,
1–13,
“DC-Coupled
1–95,
page 1–153
page 1–59
February 2011 Altera Corporation
Table
Figure
1–105,
1–5,
Table
Table
Figure
1–24,
Document Revision History
“GIGE
“Offset Cancellation
Figure
1–56,
Figure
AEQ”,
1–14,
1–77.
Links”,
1–69,
Table
Mode”.
sections.
1–6,
Figure
1–111,
Table
1–41,
“Link
Block”,
1–57,
1–16,