EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 712
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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20 000
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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2–40
Figure 2–23. Receiver Datapath Clocking in Non-Bonded Configurations Without Rate Matcher
Note to
(1) The red lines represent the FPGA fabric-Transceiver interface clock, the green lines represent the parallel recovered clock, and the blue lines
Stratix IV Device Handbook Volume 2: Transceivers
represent the serial recovered clock.
rx_coreclk[2]
rx_coreclk[3]
rx_coreclk[0]
rx_coreclk[1]
Figure
FPGA
Fabric
2–23:
FPGA Fabric-Transceiver
FPGA Fabric-Transceiver
FPGA Fabric-Transceiver
FPGA Fabric-Transceiver
Interface Clock
Interface Clock
Interface Clock
Interface Clock
Figure 2–23
without rate matcher.
In non-bonded configurations without rate matcher, the CDR in each receiver channel
recovers the serial clock from the received data. The serial recovered clock is divided
within the receiver PMA to generate the parallel recovered clock. The deserializer
uses the serial recovered clock in the receiver PMA. The parallel recovered clock and
deserialized data is forwarded to the receiver PCS. The parallel recovered clock in
each channel clocks the word aligner and 8B/10B decoder (if enabled).
hard IP
hard IP
hard IP
hard IP
PCIe
PCIe
PCIe
PCIe
Interface
rx_clkout[2]
Interface
Interface
Interface
rx_clkout[1]
rx_clkout[3]
rx_clkout[0]
PIPE
PIPE
PIPE
PIPE
shows receiver datapath clocking in non-bonded channel configurations
Compensation
Compensation
Compensation
Compensation
RX Phase
RX Phase
RX Phase
RX Phase
FIFO
FIFO
FIFO
FIFO
Ordering
Ordering
Ordering
Ordering
Byte
Byte
Byte
Byte
De-Serializer
De-Serializer
De-Serializer
De-Serializer
Byte
Byte
Byte
Byte
/2
/2
/2
/2
Ch0 Parallel Recovered Clock
Ch1 Parallel Recovered Clock
Ch3 Parallel Recovered Clock
Ch2 Parallel Recovered Clock
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
Decoder
8B/10B
Decoder
Decoder
Decoder
8B/10B
8B/10B
8B/10B
Chapter 2: Transceiver Clocking in Stratix IV Devices
Aligner
Aligner
Aligner
Aligner
Word
Word
Word
Word
Channel 0
Channel 3
Channel 1
Channel 2
Transceiver Channel Datapath Clocking
Serializer
Receiver Channel PMA
Receiver Channel PMA
Serializer
Serializer
Receiver Channel PMA
Serializer
Receiver Channel PMA
De-
De-
De-
De-
February 2011 Altera Corporation
(Note 1)
CDR
CDR
CDR
CDR
Serial Recovered Clock
Serial Recovered Clock
Serial Recovered Clock
Serial Recovered Clock
Input Reference Clock
Input Reference Clock
Input Reference Clock
Input Reference Clock
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