EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 488

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–44
Stratix IV Device Handbook Volume 2: Transceivers
In a DC-coupled link, the transmitter DC V
Link V
off-chip receiver termination and biasing circuitry must ensure compatibility between
the transmitter and the receiver V
Figure 1–38. DC-Coupled Link
Note to
(1) The receiver termination and biasing can be on-chip or off-chip.
You might choose to use the DC-coupled high-speed link for these functional modes
only:
■
■
The following sections describe DC-coupling requirements for a high-speed link with
a Stratix IV GX device used as the transmitter, receiver, or both. Specifically, the
following link configurations are described:
■
■
■
■
Basic single- and double-width
(OIF) CEI PHY interface
Stratix IV GX Transmitter (PCML) to Stratix IV GX Receiver (PCML)
Stratix II GX Transmitter (PCML) to Stratix IV GX Receiver (PCML)
Stratix IV GX Transmitter (PCML) to Stratix II GX Receiver (PCML)
LVDS Transmitter to Stratix IV GX Receiver (PCML)
Figure
CM
DC-Coupled Links
Transmitter
depends on the transmitter V
1–38:
TX Termination
TX
V
CM
CM
Physical Medium
Physical Medium
.
Figure 1–38
CM
and the receiver V
CM
Chapter 1: Transceiver Architecture in Stratix IV Devices
is seen unblocked at the receiver buffer.
shows a DC-coupled link.
RX
V
CM
February 2011 Altera Corporation
CM
RX Termination
. The on-chip or
Transceiver Block Architecture
Receiver