EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 213

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 6: I/O Features in Stratix IV Devices
Termination Schemes for I/O Standards
Figure 6–29. Differential SSTL I/O Standard Termination
February 2011 Altera Corporation
Termination
External
On-Board
Termination
OCT
Differential I/O Standards Termination
Differential SSTL Class I
Series OCT
Transmitter
Transmitter
1
50 Ω
Stratix IV devices support differential SSTL-18 and SSTL-2, differential HSTL-18,
HSTL-15, HSTL-12, LVDS, LVPECL, RSDS, and mini-LVDS.
Figure 6–35
Differential HSTL and SSTL outputs are not true differential outputs. They use two
single-ended outputs with the second output programmed as inverted.
Differential SSTL Class I
25 Ω
25 Ω
Z
Z
50 Ω
50 Ω
0
0
= 50 Ω
= 50 Ω
50 Ω
V TT V TT
show the details of various differential I/O terminations on these devices.
V CCIO
50 Ω
100 Ω
GND
100 Ω
100 Ω
100 Ω
V CCIO
Receiver
Receiver
GND
Series OCT
Differential SSTL Class II
Transmitter
Transmitter
25 Ω
50 Ω
25 Ω
25 Ω
V TT V TT
V TT
V TT
Differential SSTL Class II
50 Ω
50 Ω
Z
Z
0
0
50 Ω
= 50 Ω
= 50 Ω
50 Ω
50 Ω
Stratix IV Device Handbook Volume 1
50 Ω
Figure 6–29
V CCIO
V TT V TT
100 Ω
GND
100 Ω
100 Ω
100 Ω
50 Ω
V CCIO
Receiver
GND
through
Receiver
6–41