EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 878
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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5–32
Figure 5–18. Option 2 for Transmitter Core Clocking (Channel and CMU PLL Reconfiguration Mode)
Stratix IV Device Handbook Volume 2: Transceivers
FPGA Fabric
tx_clkout[0]
tx_clkout[1]
tx_clkout[2]
tx_clkout[3]
1
High-speed serial clock generated by the CMU0 PLL
Low-speed parallel clock generated by the local divider of the transceiver
Figure 5–18
to the Transmit Phase Compensation FIFOs of the respective transceiver channels.
Receiver core clocking refers to the clock that is used to read the parallel data from the
Receiver Phase Compensation FIFO into the FPGA fabric. You can use one of the
following clocks to read from the Receive Phase Compensation FIFO:
■
■
The Clocking/Interface screen is not available for PMA-only channels.
rx_coreclk—You can use a clock of the same frequency as rx_clkout from the
FPGA fabric to provide the read clock to the Receive Phase Compensation FIFO. If
you use rx_coreclk, it overrides the rx_clkout options in the ALTGX
MegaWizard Plug-In Manager.
rx_clkout—The Quartus II software automatically routes rx_clkout to the FPGA
fabric and back into the Receive Phase Compensation FIFO.
shows how each transmitter channel’s tx_clkout signal provides a clock
TX0 (3 Gbps/1.5 Gbps)
TX1 (3 Gbps/6 Gbps)
TX2 (3 Gbps/1.5 Gbps)
TX3 (3 Gbps)
Transciever Block
RX1
RX2
RX3
RX0
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
CMU1 PLL
CMU0 PLL
February 2011 Altera Corporation
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