EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 622

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–178
Figure 1–144. OC-48 Byte Ordering in Automatic Mode
Stratix IV Device Handbook Volume 2: Transceivers
rx_syncstatus
Deserializer
From Byte
1
rx_dataout
rx_dataout
rx_clkout
(MSB)
(LSB)
The PAD character is defaulted to the A1 byte of the A1A2 alignment pattern.
SDI Mode
The Society of Motion Picture and Television Engineers (SMPTE) defines various SDI
standards for transmission of uncompressed video.
The following three SMPTE standards are popular in video broadcasting applications:
■
■
■
You can configure Stratix IV GX and GT transceivers in HD-SDI or 3G-SDI
configuration using the ALTGX MegaWizard Plug-In Manager.
Table 1–66
SDI mode.
Table 1–66. ALTGX Configurations in SDI Mode
Notes to
(1) Not supported by Stratix IV GT devices.
(2) Stratix IV GT devices only support the 3G configuration.
Configuration
A1
X
SMPTE 259M standard—more popularly known as the standard-definition (SD)
SDI, is defined to carry video data at 270 Mbps
SMPTE 292M standard—more popularly known as the high-definition (HD) SDI,
is defined to carry video data at either 1485 Mbps or 1483.5 Mbps
SMPTE 424M standard—more popularly known as the third-generation (3G) SDI,
is defined to carry video data at either 2970 Mbps or 2967 Mbps
HD
3G
A1
A1
(2)
(1)
Table
lists the ALTGX configurations supported by Stratix IV transceivers in
1–66:
A2
A1
Data Rate (Mbps)
A2
A2
1483.5
1485
2970
2967
D0
A2
D2
D1
REFCLK Frequencies
Ordering
Block
Byte
74.175, 148.35
rx_syncstatus
rx_byteorderalignstatus
148.35, 296.7
74.25, 148.5
148.5, 297
(MHz)
A1
X
Chapter 1: Transceiver Architecture in Stratix IV Devices
A1
A1
Pad
A1
Only 20-bit interface allowed in 3G
Only 20-bit interface allowed in 3G
A2
A2
FPGA Fabric-Transceiver
February 2011 Altera Corporation
To PLD Core
Interface Width
10 bit and 20 bit
10 bit and 20 bit
Transceiver Block Architecture
D1
D0
D3
D2