EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 902

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

5–56
Stratix IV Device Handbook Volume 2: Transceivers
1
1
Central Control Unit Reconfiguration Mode Details
Central control unit reconfiguration mode is a .mif-based mode used to reconfigure
the central control unit (CCU) of the transceiver. Use reconfig_mode_sel[] to activate
this mode. Central control unit reconfiguration mode is applicable for bonded PCS
configurations such as Basic ×4 and ×8, XAUI, and PCIe ×4 and×8. For the allowed
configurations, refer to
For instance, to dynamically reconfigure an ALTGX instance in Basic ×4 configuration
to a XAUI configuration, you must first configure:
1. The transceiver channel and CMU PLL to run at the XAUI data rate and functional
2. Reconfigure the central control unit portion of the transceiver from Basic to XAUI
Dynamic reconfiguration is not available if hard IP is used in PCIe mode.
To switch between one bonded PCS configuration and another, always use:
Special Guidelines
The following section describes the special guidelines required for the transceiver
channel reconfiguration modes previously described. This section includes the
following:
■
■
■
Guidelines for Re-Using .mifs
To configure the transceiver PLLs and receiver CDRs for multiple data rates, it is
important to understand the input reference clock requirements. This helps you to
efficiently create the clocking scheme for reconfiguration and to reuse the .mifs across
all channels in the device. This section describes the clocking enhancements and the
implications of using input clocks from various clock sources.
The available clock inputs appear as a pll_inclk_rx_cruclk[] port and can be
provided from the inter-transceiver block lines (also known as ITB lines), from the
global clock networks that are driven by an input pin or by a PLL cascade clock.
mode (use channel and CMU PLL reconfiguration mode).
functional mode (use central control unit reconfiguration mode). For more
information about the central control unit reconfiguration mode, refer to
2” on page
1) Channel and CMU PLL reconfiguration mode followed by
2) Central control unit reconfiguration mode
Use the same .mif for both the these steps. In step 1, a partial .mif is written and
the remaining contents of the .mif is written in step 2. In step 1, reconfigure all the
channels one-by-one. In step-2, reconfiguration of the central control unit is
transceiver-block based. Reconfigure any one of the four channels in the
transceiver block.
“Guidelines for Re-Using .mifs” on page 5–56
“Guidelines for logical_tx_pll_sel and logical_tx_pll_sel_en Ports” on page 5–58
“Guidelines for Specifying the Input Reference Clocks” on page 5–60
5–98.
Table 5–5 on page
5–19.
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
February 2011 Altera Corporation
“Example