EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 935

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Duration
Dynamic Reconfiguration Duration
February 2011 Altera Corporation
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Dynamic reconfiguration duration is the number of cycles the busy signal is asserted
when the dynamic reconfiguration controller performs write transactions, read
transactions, or offset cancellation of the receiver channels.
PMA Controls Reconfiguration Duration
The following section contains an estimate of the number of reconfig_clk clock
cycles the busy signal is asserted during PMA controls reconfiguration using
Method 1, Method 2, or Method 3. For more information, refer to
Reconfiguring PMA Controls” on page 5–13
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Enable self recovery option—When you select this option, the controller
automatically recovers if the operation did not complete within the expected time.
The error signal is driven high whenever the controller performs a self recovery.
TX Data Rate Switch using Local Divider-write operation without input port
option:
TX Data Rate Switch using Local Divider- read operation without output
port option:
Channel and/or TX PLL reconfig/select-read operation option:
Adaptive Equalization option—read operation:
EyeQ option—read operation:
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The rate_switch_ctrl input port is not used
The reconfig_mode_sel port is set to 3 (if other reconfiguration mode
options are selected in the Reconfiguration settings screen)
The write_all signal is asserted
The rate_switch_out output port is not used
The reconfig_mode_sel port is set to 3 (if other reconfiguration mode
options are selected in the Reconfiguration settings screen)
The read signal is asserted
The reconfig_mode_sel input port is set to 4, 5, 6, or 7
The read signal is asserted
The reconfig_mode_sel input port is set to 7, 8, 9, or 10
The read signal is asserted
The reconfig_mode_sel input port is set to 11
The read signal is asserted
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Stratix IV Device Handbook Volume 2: Transceivers
“Dynamically
5–89