EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 501

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–46. Interface of Offset Cancellation Control Logic to the ALTGX Instance
February 2011 Altera Corporation
reconfig_clk
busy
f
1
1
ALTGX_RECONFIG Instance
Offset Cancellation
Dynamic Re-config
Offset cancellation is executed automatically once each time a Stratix IV GX and GT
device is powered on (after the device has finished programming and switches to user
mode as indicated by CONFIG_DONE=1). The control logic for offset cancellation is
integrated into the ALTGX_RECONFIG megafunction. The reconfig_fromgxb and
reconfig_togxb buses and the necessary clocks must be connected between the
ALTGX instance and the ALTGX_RECONFIG instance.
You must reprogram your device to restart the Offset Cancellation process.
For more information about offset cancellation control logic connectivity, refer to the
Dynamic Reconfiguration in Stratix IV Devices
During offset cancellation, signified by a high on the busy signal, rx_analogreset is
not relevant until the busy signal goes low.
Offset cancellation logic requires a separate clock. In PCIe mode, you must connect
the clock input to the fixedclk port provided by the ALTGX MegaWizard Plug-In
Manager. The frequency of this clock input must be 125 MHz. For all other functional
modes, connect the clock input to the reconfig_clk port provided by the ALTGX
MegaWizard Plug-In Manager. The frequency of the clock connected to the
reconfig_clk port must be within the range of 37.5 to 50 MHz.
interface of the offset cancellation control logic (ALTGX_RECONFIG instance) and the
ALTGX instance.
The offset cancellation process begins by disconnecting the path from the receiver
input buffer to the receiver CDR. It then sets the receiver CDR into a fixed set of
dividers to guarantee a VCO clock rate that is within the range necessary to provide
proper offset cancellation. Subsequently, the offset cancellation process goes through
various states and culminates in the offset cancellation of the receiver buffer and the
receiver CDR.
logic
Logic
reconfig_fromgxb
reconfig_togxb
reconfig_clk
chapter.
Stratix IV Device Handbook Volume 2: Transceivers
ALTGX Instance with 4 Channels
Transceiver Block
Buffer
Buffer
Buffer
Buffer
Figure 1–46
TX
RX
TX
RX
TX
RX
TX
RX
CDR
CDR
CDR
CDR
shows the
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