EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 633
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SE230F29C3N PDF datasheet #6
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Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Table 1–68. FPGA Fabric-PMA Interface Widths and Data Rates Supported in Basic (PMA Direct) ×1/×N Single-Width and
Double-Width Modes for Stratix IV GX and GT Devices
February 2011 Altera Corporation
Functional Mode
×1/×N
Single-width
mode
×1/×N
Double-width
mode
(PMA Direct)
Basic
f
f
f
Interface Width
Fabric-PMA
Table 1–68
supported in Basic (PMA Direct) ×1/×N single-width and double-width modes.
Basic (PMA Direct) ×1 Configuration
You can configure a transceiver channel in this mode by setting the which protocol
will you be using? field to Basic (PMA Direct) and the which sub protocol will you
be using? field to none. In this configuration, the Quartus II software requires one of
the two CMU PLLs within the same transceiver block to provide high-speed clocks to
the transmitter side of the channel.
If the CMU0 or CMU1 channel is configured in Basic (PMA Direct) ×1 configuration, use
their local clock dividers to provide clock to their respective transmitter channels.
For information about clocking restrictions in Basic (PMA Direct) ×1 mode, refer to
the “Non-Bonded Basic (PMA Direct) Mode Channel Configurations” section in the
Transceiver Clocking in Stratix IV Devices
For information about routing the clocks to transceiver channels in Basic
(PMA Direct) ×1 mode, refer to the
Basic (PMA Direct) ×N Configuration
You can configure a transceiver channel in this mode by setting the which protocol
will you be using field to Basic (PMA Direct) and the which sub protocol will you
be using field to ×N. In this mode, all the transmitter channels can receive their
high-speed clock from the CMU0 PLL from the transceiver blocks or the ATX PLL
present on the same side of the device. These clocks are provided through the ×N_Top
or ×N_Bottom clock line.
In this mode, if you use a CMU PLL to generate the transceiver channel datapath
interface clocks, only the CMU0 central clock divider of the transceiver block containing
the CMU PLL is used.
For information about clocking restrictions in Basic (PMA Direct) ×N mode, refer to
the “Non-Bonded Basic (PMA Direct) Mode Channel Configurations” section in the
Transceiver Clocking in Stratix IV Devices
10 bit
16 bit
20 bit
FPGA
8 bit
lists the Stratix IV GX and GT PLD-PMA interface widths and data rates
C2 Speed Grade
0.6 Gbps to
0.6 Gbps to
1.0 Gbps to
1.0 Gbps to
3.25 Gbps
2.6 Gbps
5.2 Gbps
6.5 Gbps
C3/I3 Speed Grade
Stratix IV GX
Transceiver Clocking in Stratix IV Devices
0.6 Gbps to
0.6 Gbps to
1.0 Gbps to
1.0 Gbps to
3.25 Gbps
2.6 Gbps
5.2 Gbps
6.5 Gbps
Supported Data Rate Range
chapter.
chapter.
Stratix IV Device Handbook Volume 2: Transceivers
C4 Speed Grade
0.6 Gbps to
0.6 Gbps to
1.0 Gbps to
1.0 Gbps to
3.25 Gbps
2.6 Gbps
5.0 Gbps
5.0 Gbps
Stratix IV GT
600 Mbps to
600 Mbps to
1.0 Gbps to
1.0 Gbps to
3.25 Gbps
I1, I2, I3
2.6 Gbps
5.2 Gbps
6.5 Gbps
chapter.
1–189
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