EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 913

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
February 2011 Altera Corporation
1
1
When the device powers up, the dynamic reconfiguration controller initiates offset
cancellation on the receiver channel by disconnecting the receiver input pins from the
receiver data path. It also sets the receiver CDR into a fixed set of dividers to
guarantee a voltage controlled oscillator (VCO) clock rate within the range necessary
to provide proper offset cancellation. Subsequently, the offset cancellation process
goes through different states and culminates in the offset cancellation of the receiver
buffer and receiver CDR. After offset cancellation is complete, the user divider
settings are restored.
The dynamic reconfiguration controller sends and receives data to the transceiver
channel through the reconfig_togxb and reconfig_fromgxb signals. You must
connect these signals between the ALTGX_RECONFIG instance and the ALTGX
instance. You must also set the What is the number of channels controlled by the
reconfig controller? option in the Reconfiguration settings screen of the
ALTGX_RECONFIG MegaWizard Plug-In Manager. For more information, refer to
“Total Number of Channels Option in the ALTGX_RECONFIG Instance” on
page
The Use 'logical_channel_address' port for Analog controls reconfiguration option
in the Analog controls screen of the ALTGX_RECONFIG MegaWizard Plug-In
Manager is not applicable for the receiver offset cancellation process.
If the design does not require PMA controls reconfiguration and uses optimum logic
element (LE) resources, you can connect all the ALTGX instances in the design to a
single dynamic reconfiguration controller (ALTGX_RECONFIG instance).
The gxb_powerdown signal must not be asserted during the offset cancellation
sequence.
To understand the impact on system start-up when you control all the transceiver
channels using a single dynamic reconfiguration controller, refer to
Reconfiguration Duration” on page
ALTGX_RECONFIG Instance Signals Transition during Offset Cancellation
Consider that the design has ALTGX instances with channels of both Transmitter
only and Receiver only configurations. You must include the Transmitter only
channels while setting the What is the starting channel number? option in the
ALTGX instance and setting the What is the number of channels controlled by the
reconfig controller? option in the ALTGX_RECONFIG instance for receiver offset
cancellation.
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After the device powers up, the busy signal remains low for the first reconfig_clk
clock cycle.
The busy signal then gets asserted for the second reconfig_clk clock cycle when
the dynamic reconfiguration controller initiates the offset cancellation process.
The de-assertion of the busy signal indicates the successful completion of the offset
cancellation process.
5–10.
5–89.
Stratix IV Device Handbook Volume 2: Transceivers
“PMA Controls
5–67