EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 301

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Receiver
Figure 8–18. Receiver Data Path in Non-DPA Mode
Notes to
(1) In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
(2) The rx_out port has a maximum data width of 10 bits.
February 2011 Altera Corporation
rx_divfwdclk
rx_outclock
Fabric
FPGA
Figure
rx_out
8–18:
f
1
10
When using non-DPA receivers, you must drive the PLL from a dedicated and
compensated clock input pin. Compensated clock inputs are dedicated clock pins in
the same I/O bank as the PLL.
For more information about dedicated and compensated clock inputs, refer to the
Clock Networks and PLLs in Stratix IV Devices
IOE Supports SDR, DDR, or Non-Registered Datapath
(LOAD_EN, diffioclk)
2
Deserializer
DOUT DIN
IOE
2
Left/Right PLL
3
DOUT DIN
Clock Mux
Bit Slip
(LVDS_LOAD_EN,
(Note
LVDS_diffioclk,
rx_outclk)
diffioclk
1),
(2)
rx_inclock
chapter.
8 Serial LVDS
Clock Phases
Synchronizer
DOUT DIN
L L
LVDS Receiver
N
3
(DPA_LO
Stratix IV Device Handbook Volume 1
DPA_diffioclk,
rx_divfwdclk)
P P
P P
AD_EN,
DPA Circuitr
Retimed
DPA Cloc
LVDS Clock Domain
P P
P P
Data
k
DIN
y
+
rx_in
8–23