EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 270

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

7–50
Figure 7–31. Stratix IV IOE Input Registers
Notes to
(1) You can bypass each register block in this path.
(2) This is the 0-phase resynchronization clock (from the read-leveling delay chain).
(3) The input clock can be from the DQS logic block (whether the postamble circuitry is bypassed or not) or from a global clock line.
(4) This input clock comes from the CQn logic block.
(5) This resynchronization clock comes from a PLL through the clock network (resync_ck_2x).
(6) The I/O clock divider resides adjacent to the DQS logic block. In addition to the PLL and read-leveled resync clock, the I/O clock divider can also
(7) The half-rate data and clock signals feed into a dual-port RAM in the FPGA core.
(8) You can dynamically change the dataoutbypass signal after configuration to select either the directin input or the output from the half data
(9) The DQS and DQSn signals must be inverted for DDR, DDR2, and DDR3 interfaces. When using Altera’s memory interface IPs, the DQS and DQSn
(10) The bypass_output_register option allows you to select either the output from the second mux or the output of the fourth alignment/
Stratix IV Device Handbook Volume 1
DQS/CQ (3), (9)
DQSn (9)
CQn (4)
be fed by the DQS bus or CQn bus.
rate register to feed dataout.
signals are automatically inverted.
synchronization register to feed dataout.
Figure
I/O Element Registers
Resynchronization Clock
7–31:
Differential
(resync_clk_2x) (5)
Input
Buffer
DQ
0
1
Double Data Rate Input Registers
The IOE registers are expanded to allow source-synchronous systems to have faster
register-to-register transfers and resynchronization. Both top and bottom and left and
right IOEs have the same capability. Left and right IOEs have extra features to support
LVDS data transfer.
Figure 7–31
consists of the DDR input registers, resynchronization registers, and HDR block. You
can bypass each block of the input path.
Input Reg A
Input Reg B
D
D
DFF
DFF
Q
Q
neg_reg_out
I
I
Input Reg C
D
DFF
Q
shows the registers available in the Stratix IV input path. The input path
datain [0]
I
Alignment & Synchronization Registers
(Note 1)
datain [1]
enainputcycledelay
D
D
DFF
DFF
Q
Q
enaphasetransferreg
D
D
DFF
DFF
Q
Q
<bypass_output_register>(10)
0
1
Divider (6)
I/O Clock
0
1
D
D
DFF
DFF
Q
Q
0
1
0
1
(2)
Chapter 7: External Memory Interfaces in Stratix IV Devices
Half-Rate Resynchronization Clock (resync_clk_1x)
D
D
DFF
DFF
Q
Q
dataout
dataout
Stratix IV External Memory Interface Features
Half Data Rate Registers
D
D
D
D
February 2011 Altera Corporation
DFF
DFF
DFF
DFF
Q
Q
Q
Q
D
D
DFF
DFF
dataout [0]
dataout [1]
To Core
Q
Q
To Core
(7)
(7)
directin
0
1
0
1
dataout [3]
dataoutbypass
To Core
(7)
dataout[2]
to core (7)
To Core
(8)
(7)